SD主机控制器简化规范4.20版解析

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"PartA2_SD Host_Controller_Simplified_Specification_Ver4.20.pdf" 是关于SDIO协议的详细规格文档，该文档是SD Host Controller简化的规范，版本4.20，由SD Association的技术委员会在2018年7月25日发布。这个规范覆盖了对SD主机控制器的最新更新，包括UHS-I I的支持、共享总线支持、ADMA3（Advanced DMA Mode 3）支持以及64位系统寻址支持。 SDIO（Secure Digital Input/Output）协议是一种用于SD卡和主机之间传输数据和控制信号的接口标准。它不仅提供了数据传输功能，还允许设备通过SD卡接口进行输入输出操作，例如Wi-Fi模块、GPS接收器或蓝牙模块等。SDIO协议扩展了传统的SD卡功能，使得单一的物理接口可以处理多种不同的I/O功能。在SD Host Controller Simplified Specification Version 4.20中，有以下几个关键点： 1. **UHS-I (Ultra High Speed Phase 1)**：这是SD卡的一个高速模式，旨在提高数据传输速率。UHS-I支持更高的总线速度，如104MB/s（UHS-1 Class 1）和312MB/s（UHS-1 Class 3），以满足高清视频和其他大数据量应用的需求。 2. **Shared Bus Support**：此特性允许多个SD或SDIO设备共享同一总线，从而节省系统资源并简化硬件设计。通过时分复用技术，可以在不同设备间切换，实现多设备同时通信。 3. **ADMA3 (Advanced DMA Mode 3)**：高级直接存储访问模式3是SD主机控制器的一种增强数据传输方式，它允许更高效的数据处理，减少了CPU的参与，提高了数据吞吐量和系统的整体性能。 4. **64-bit System Addressing Support**：这一更新意味着SD主机控制器现在能够支持64位地址空间，显著扩大了可寻址内存，对于处理大量数据的应用尤其有利，如高清视频录制和播放。 5. **Revised Disclaimers**：2018年的修订版可能包含了一些法律免责声明的更新，确保了规范的使用符合SD Association的规定和版权要求。 SD Host Controller Simplified Specification Version 4.20是SDIO设备开发者和硬件工程师的重要参考资料，它详细规定了SD主机控制器如何与SDIO设备交互，以实现高速、高效且灵活的数据传输和设备控制。这个规范的更新反映了SD技术的持续演进，以适应不断增长的存储和I/O需求。

SD Host Controller Simplified Specification Version 4.20

1.3 Multiple Slot Support

One Standard Register Set is defined for each slot. If the Host Controller has two slots, two register sets

is required. Each slot is controlled independently. This enables support for combinations of bus interface

voltage, bus timing and SD Clock frequencies.

Figure 1-3 : Register Map for Multiple Slots Controller

Figure 1-3 shows the register map for a multiple slot Host Controller. The Host Driver shall determine

the number of slots and base pointers to each slot's Basic Register Set using PCI Configuration register

or vendor specific methods. Offsets from 0F0h to 0FFh are reserved for the Common register area that

defines information for slot control and common status. The common register area is accessible from

any slot's register set. This allows software to control each slot independently, since it has access to the

Slot Interrupt Status register and the Host Controller Version register from each register set. From 100h

to mFFh, Extended Register Set can be assigned. A parameter "m" denotes integer to determine size of

the Extended Register Set.

1.4 Supporting DMA

The Host Controller provides a "programmed I/O" method for the Host Driver to transfer data using the

Buffer Data Port register. Optionally, Host Controller implementers may support data transfer using

DMA. The DMA algorithm defined in the SD Host Controller Standard Specification Version 1.00 is

called SDMA (Single Operation DMA). Only one SD command transaction can be executed per an

SDMA operation. Support of SDMA can be checked by the SDMA Support in the Capabilities register.

This specification defines a DMA transfer algorithm called ADMA (Advanced DMA). ADMA provides data

transfer between system memory and SD card without interruption of CPU execution. Support of ADMA

can be checked by the Capabilities register. Refer to Section 1.13 for more details about ADMA. When

the term "DMA" is used in this document, it applies to both SDMA and ADMA.

Prior to using DMA, the Host Driver shall confirm that both the Host Controller and the system bus

support it (PCI bus can support DMA). DMA shall support both single block and multiple-block transfers.

Host Controller registers shall remain accessible for issuing non-DAT line commands during a DMA

transfer execution (Not applicable to UHS-II mode). The result of a DMA transfer shall be the same

regardless of the system bus data transfer method.

The Host Driver can stop and restart a DMA operation by the control bits in the Block Gap Control

setting Continue Request, DMA operation can be restarted. Refer to the Block Gap Control register for

more details. If an error occurs, DMA operation shall be stopped. Synchronous abort described in

Section 3.8.3 should be used to abort DMA transfer instead of asynchronous abort to ensure

Basic

for Slot n

Base Pointer 1

000h

0EFh

Base Pointer 2

Basic

for Slot 2

Base Pointer n

Common Register Area

0FFh-0F0h

Slot 1

Slot 2

Slot n

Basic

for Slot 1

Extended

for Slot 1

100h

mFFh

Extended

for Slot 2

Extended

for Slot n

SD Host Controller Simplified Specification Version 4.20

cancellation of DMA does not affect system bus operation. Stop operating DMA by using Stop At Block

Gap Request and then issue abort command to stop card data transfer. After that, Host Driver resets

the Host Controller by using the Software Reset For DAT Line in the Software Reset register (SD

mode) or the Host SD-TRAN Reset in the UHS-II Software Reset register (UHS-II mode).

1.5 SD Command Generation

1.5.1 SD Mode Command Generation

SDMA

Command

ADMA

Command

CPU data

Transfer

Non-DAT

Transfer

32-bit Block Count /

(SDMA System Address)

Note 1

Note 1,2,3

No (Protected)

Block Size

Yes

No (Protected)

16-bit Block Count

Note 3

Refer to 1.15.3

Note 3

No (Protected)

Argument

Yes

Transfer Mode

Yes

Note 4

Command

Yes

Note 1: If Host Version 4 Enable is set to 1 in the Host Control 2 register, this register is used for 32-bit Block

Count instead of SDMA System Address. SDMA start address is moved to ADMA System Address

Note 2: Auto CMD23 is supported from Version 3.00 and setting of this register is set to the argument of CMD23

when Auto CMD23 is executed. If Host Version 4 Enable =0, Auto CMD23 cannot be used with SDMA.

Host Controller Version 4.10 re-defines this register as 32-bit Block Count so that all data transfer modes

may use 32-bit Block Count when Host Version 4 Enable =1.

Note 3: Version 2.00 or later uses 16-bit Block Count register or ADMA2 total length to determine transfer length.

Additionally, Version 4.10 may use 32-bit Block Count register, which is selected when Host Version 4

Enable is set to 1 and 16-bit Block Count is set to 0000h.

Note 4: If Host Version 4 Enable = 0, “No (Protected)”. If Host Version 4 Enable = 1, “Yes”.

Table 1-2 : Registers to Generate SD Command

Table 1-2 shows register settings (at offsets from 000h to 00Fh in the register set) necessary for three

types of transactions: SDMA generated transfers, ADMA generated transfers, CPU data transfers (using

"programmed I/O") and non-DAT transfers. When initiating a transaction, the Host Driver should

program these registers sequentially from 000h to 00Fh. The beginning register offset may be

calculated based on the type of transaction. The last written offset shall be always 00Fh because writing

to the upper byte of the Command register shall trigger issuance of an SD command.

The Host Driver should not read the SDMA System Address, Block Size and Block Count registers

during a data transaction unless the transfer is stopped because the value is changing and not stable.

To prevent destruction of registers using data transfer when issuing command, the 32-bit Block Count,

Block Size, 16-bit Block Count and Transfer Mode registers shall be write protected by the Host

Controller while Command Inhibit (DAT) is set to 1 in the Present State register. (When Host Version 4

Enable =0, the SDMA System Address is not protected by this signal.) The Host Driver shall not write

the Argument and Command registers while Command Inhibit (CMD) is set to 1.

1.5.2 UHS-II Mode Command Generation

UHS-II Command Packet is generated by setting following registers.

(1) UHS-II Block Size Register for DCMD

(2) UHS-II Block Count Register for DCMD

(3) UHS-II Command Packet Register for CCMD and DCMD

(4) UHS-II Transfer Mode Register for CCMD and DCMD

(5) UHS-II Command Register for CCMD and DCMD

SD Host Controller Simplified Specification Version 4.20

Theses registers are correspondent to that of SD Mode registers. UHS-II command packet image is set

to UHS-II Command Packet register. Host Controller does not analyze this register to issue a command

packet. On writing to UHS-II Command register, Host Controller issues a command packet.

1.5.2.1 Command Issuing during CTS

When CCMD is issued at CTS of DCMD execution, the RES packet of CCMD is set to the UHS-II

Response register. If CCMD is other than reset or abort command, DCMD execution continues. For

example, this feature may be used for issuing CMD52 during CMD53 execution in case of SDIO. Refer

to Section 1.17 for more details about response error check.

1.5.2.2 Support of TID Check

Host Controller Version 4.10 supports TID. Host Controller compares TID of command with TID of all

received packets of the same transaction. If TID is not matched, TID Error is set to 1 in the UHS-II Error

Interrupt Status register and the transaction shall be stopped.

In case of command issuing during CTS, it works if TID in DCMD and TID in CCMD during CTS are set

to 0. It also works if different values other than 0 are set to them.

1.6 Suspend and Resume Mechanism (Version 3.00 or less)

Suspend/Resume function is not supported from Version 4.00.

Figure 1-4 : Suspend and Resume Mechanism

Support for Suspend/Resume can be determined by checking Suspend/Resume Support in the

Capabilities register. When the SD card accepts a suspend request, the Host Driver saves information

in the first 14 bytes registers (that is, offsets 000h-00Dh) before issuing other SD commands. On

resuming, the Host Driver restores these registers and then issues the Resume command to continue

suspended operation.

The SDIO card sets the DF (Resume Data Flag) in the response to the Resume command. (Since the

Suspend and Resume commands are CMD52 operations, the response data is actually the Function

Select Register in the CCCR.) If DF is set to 0, it means the SDIO card cannot continue data transfer

while suspended. This bit can be used to control data transfers and interrupt cycles. If the Resume Data

Flag is set to 0, no more data is transferred and an interrupt cycle is started if the transaction being

resumed is in 4-bit mode. If DF is set to 1, data transfers continue. The Suspend/Resume protocol is

described in the SDIO Specification (SD Specifications Part E1).

Note: To use Suspend/Resume function, it is necessary that SDIO Card supports the Suspend and

Resume commands and Read Wait control.

Saving

Restoring

Issue data transfer

command

Issue

Suspend Command

Transfer

data block

Issue

Resume Command

Transfer

data block

Issue data transfer

command

Transfer

data block

Accepted

Insert another

data transfer

000-00D

SD Host Controller Simplified Specification Version 4.20

1.7 Buffer Control

The Host Controller has a data buffer for data transfer. The Host Driver accesses internal buffer through

the 32-bit Buffer Data Port register. DMA also uses internal buffer to control data transfer between

system memory and SD Card.

Buffer Size is determined by setting of block size. Data Transfer Size is determined by setting of block

size and block count.

In SD mode, block size is set by Block Size register (Offset 004h) and block count is set by 16-bit Block

Count register (Offset 006h). 16-bit block count limits the maximum data transfer length. The buffer size

is determined by setting of the Block Size register.

In UHS-II mode, block size is set by UHS-II Block Size register (Offset 080h) and block count is set by

32-bit UHS-II Block Count register (Offset 084h). There is no limit of data transfer length by 32-bit block

count. The buffer size is determined by setting of the Block Size register and N_FCU in the UHS-II

Settings register as follows:

Buffer Size in UHS-II mode = UHS-II Block Size * N_FCU (Settings)

Followings Sections show some rules to access the buffer.

1.7.1 Control of Buffer Pointer (Non DMA)

Internally, the Host Controller maintains a pointer to control the data buffer. The pointer is not directly

accessible by the Host Driver. Every time the Buffer Data Port register is accessed, the pointer is

incremented depending on amount of data written to the buffer. In order to accommodate a variety of

system busses, this pointer shall be implemented regardless of system bus width (8-bit, 16-bit, 32-bit or

64-bit system bus width can be supported). To specify control of the pointer, the Host Controller data

buffer interface shall have the following characteristics:

(6) System Bus Width and Byte Enable Address

8-bit, 16-bit, 32-bit or 64-bit system bus is supported. To specify byte position for Buffer Data Port

between lower address and byte enable depending on system bus width. The Buffer Data Port

System Bus

A[02]

A[01]

A[00]

BE[3]

D[31:24]

BE[2]

D[23:16]

BE[1]

D[15:08]

BE[0]

D[07:00]

64-bit

Yes

32-bit

Yes

16-bit

Yes

8-bit

Yes

"Yes" means the signal is used for control and "No" means the signal is not used.

: BE[00] for 8-bit bus is always 1 therefore it may not be defined.

Table 1-3 : Relations between Address and Byte Enable

(7) Sequential and continuous access

The Buffer Data Port register shall be accessed by sequential and continuous manner. The buffer

pointer is controlled by the Byte Enable patterns when accessing to the Buffer Data Port register.

Therefore, Byte Enable patterns shall be sequential and continuous as well. The order of Byte

Enable is according to little endian format. For example, BE[1] is accessed, next access shall

start form BE[2]. Random or skipped access is not allowed.

Table 1-4 shows possible byte enables patterns that shall be supported by the Host Controller.

However, if the system controller supports write merge, it may generate the other byte enable

patterns. To avoid generating unsupported byte enable patterns for the 32-bit or 64-bit bus

SD Host Controller Simplified Specification Version 4.20

system, the Host Driver is allowed to use word or double word access to the Buffer Data Port

OK BE[3:0]=0011b (2-byte) => BE[3:0]=1100b (2-byte) => BE[3:0]=0011b (2-byte)

OK BE[3:0]=1100b (2-byte) => BE[3:0]=1111b (4-byte) => BE[3:0]=0011b (2-byte)

OK BE[3:0]=1111b (4-byte) => BE[3:0]=1111b (4-byte) => BE[3:0]=1111b (4-byte)

Not OK BE[3:0]=0011b (2-byte) => BE[3:0]=0011b (2-byte) (Cannot skip BE[2],BE[3])

Not OK BE[3:0]=0011b (2-byte) => BE[3:0]=1111b (4-byte) (Cannot skip BE[2],BE[3])

Byte Enable

BE[3]

BE[2]

BE[1]

BE[0]

Data Bus

D[31:24]

D[23:16]

D[15:08]

D[07:00]

Access

Type

4-byte

2-byte

1-byte

* 1 means BE is valid and 0 means BE is not valid.

Table 1-4 : Available Byte Enable Pattern for Buffer Data Port Register

(8) Buffer Control with Block Size

The buffer preserves data up to the block size specified by the Block Size register. Following

definitions of controlling buffer enable the Host Driver to access the Buffer Data Port register

repeatedly with 32-bit width regardless of block size.

In case of write operation, the buffer accumulates the data written through the Buffer Data Port

State register changes 1 to 0. It means no more data can be written to the buffer. Excess data of

the last write is ignored. For example, if just lower 2 bytes data can be written to the buffer and a

32-bit (4-byte) block of data is written to the Buffer Data Port register, the lower 2 bytes of data is

written to the buffer and the upper 2 bytes is ignored. Every time Buffer Write Enable changes 0

to 1, it means a next block of data can be written to the buffer. A new blocks write shall always

start from BE[00] position. After that, a block of data can be written to the buffer without checking

Buffer Write Enable.

In case of read operation, every time Buffer Read Enable in the Present State register changes

0 to 1, a block of data can be read through the Buffer Data Port register. A new block read shall

always start from BE[00] position. After that, a block of data can be read from the buffer without

checking Buffer Read Enable. Excess data of the last read is ignored. For example, if just lower

2 bytes of data are left in the buffer and a 32-bit (4-byte) read is performed, the lower 2 bytes is

valid but the upper 2 bytes is undefined. When the buffer pointer reaches block size, Buffer Read

Enable changes 1 to 0. It means no more data can be read from the buffer.

Implementation Note:

Table 1-4 implies that the Host Driver should align register accesses on address boundaries

matching the number of bytes in the access. That is, single byte accesses may be aligned on

any offset within the register set; word (double byte) accesses should be aligned on two-byte

offsets; and double-word (quad byte) accesses should be aligned on four-byte offsets. According

to the feature (3), the Host Driver can always access Buffer Data Port register with double-word

access.

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SD主机控制器简化规范4.20版解析

SD-Host-Controller-Simplified-SpecificationV4.20.pdf

PartE1_SDIO_Simplified_Specification_Ver2.00.pdf

Part A2 SD Host Controller Standard Specification Ver3

part1_physical_layer_simplified_specification_ver6.00

如何在嵌入式系统中实现SD HC V4.2标准的高速数据传输功能？请结合《SD-Host-Controller-Simplified-SpecificationV4.20.pdf》进行说明。

在嵌入式系统中实现SD HC V4.2标准的高速数据传输功能，具体需要遵循哪些步骤和关键技术点？

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