TI ADS7138：8通道I2C ADC模块，GPIO和CRC功能详解

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TI-ADS7138是一款高性能的8通道12位ADC（模拟到数字转换器），专为紧凑型设计而优化。该器件具有以下重要特点： 1. 尺寸优势：采用3mm×3mm的WQFN封装，节省空间的同时确保了模块化集成。 2. 多功能接口：支持8个模拟输入通道，这些通道可以根据需求灵活配置，可以作为模拟输入、数字输入或者数字输出，增强了信号处理和扩展能力。GPIO功能支持开漏和推挽输出，方便实现I/O扩展。 3. 模拟监控与保护：每个模拟输入通道配备可编程阈值，用于监测电压并在达到预设阈值时触发事件，有助于瞬态抑制和系统保护。此外，设备还具备事件计数器，增强系统稳定性。 4. 宽广的工作范围：AVDD工作电压支持2.35V至5.5V，DVDD则可以从1.65V至5.5V，适应不同应用场合的供电需求。温度范围广泛，适用于-40°C至+125°C的极端环境。 5. 数据校验功能：集成CRC（循环冗余校验）技术，确保数据读取和写入的准确性，包括上电配置时的数据完整性检查，提高了通信可靠性。 6. 快速I2C接口：最高可达3.4MHz的传输速率，支持高速通信，适合实时数据交换。 7. 设备控制：通过Sequencer功能实现数据采集序列控制，提高系统效率。此外，I2C接口允许用户通过外部总线进行设备配置和通信。 8. 电源管理：包括内置的OVP（过电压保护）和OCP（过电流保护）机制，确保设备在异常条件下的安全运行。 9. 产品支持：文档详细介绍了产品概述、技术规格、工具软件、支持资源和社区服务，为用户提供全方位的技术指导。 TI-ADS7138是一款功能强大且易于集成的ADC解决方案，尤其适合对小型化、高精度和高效能要求的应用场景，如工业自动化、物联网设备和消费电子等。在使用前，务必查阅最新的英文版数据手册以获取最准确的产品信息。

ADVANCEINFORMATION

ADS7138

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ZHCSJS8 –MAY 2019

8.3.7 CRC on Data Interface

The ADS7138 features a cyclic redundancy check (CRC) module for checking the integrity of the data bits

exchanged over the I

C interface. The CRC module is bidirectional and appends an 8-bit CRC to every byte read

from the device while also evaluating the CRC of every incoming byte over the I

C interface. The CRC module

uses the CRC-8-CCITT polynomial (x

+ x

+ x + 1) for CRC computation.

To enable the CRC module, set the CRC_EN bit in the GENERAL_CFG register. 表 3 shows how a CRC error

can be detected when configuring the ADS7138.

表表 3. Configuration Notifications When a CRC Error is Detected

CRC ERROR NOTIFICATION CONFIGURATION DESCRIPTION

ALERT pin ALERT_CRCIN = 1b ALERT pin is asserted if a CRC error is detected by the device.

Status flags APPEND_STATUS = 10b

4-bit status flags are appended to the ADC data; see the Output Data

Format section for details.

When the ADS7138 detects a CRC error, the erroneous data are ignored and the CRC_ERR_IN bit is set. 表 3

describes the additional notifications that can be enabled. Further register writes are disabled until the

CRC_ERR_IN bit is cleared by writing 1b to it. When using autonomous mode, further conversions can be

disabled on the CRC error by setting CONV_ON_ERR to 1b; see the Autonomous Mode section.

8.3.8 General-Purpose I/Os (GPIOs)

The eight channels of the ADS7138 can be independently configured as analog inputs, digital inputs, or digital

outputs. 表 4 describes how the PIN_CFG and GPIO_CFG registers can be used to configure the channels.

表表 4. Configuring Channels as Analog Inputs or GPIOs

PIN_CFG[7:0] GPIO_CFG[7:0]

GPO_DRIVE_CF

G[7:0]

CHANNEL CONFIGURATION

0 x x Analog input (default)

1 0 x Digital input

1 1 0 Digital output; open-drain driver

1 1 1 Digital output; push-pull driver

The digital outputs can be configured to logic 1 or 0 by writing to the GPO_OUTPUT_VALUE register. Reading

the GPI_VALUE register returns the logic level for all channels configured as digital inputs.

ADVANCEINFORMATION

ALERT_CH_SEL[7]

EVENT_RGN[7]

ADC

Averager

1 to 128

12-bit ADC data

[15:4] Average result

High threshold -

Hysteresis

Event

Counter

EVENT_HIGH_FLAG

EVENT_LOW_FLAG

Low threshold +

Hysteresis

ALERT_CH_SEL[0]

All registers are specific for

individual analog input channels

ALERT

EVENT_RGN[0]

MUX

Digital input CH0

PIN_CFG

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 A

D11 D10 D9 D8 D7 D6 D5 D4A AD3 D2 D1 D0D12D13D14D15

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 0 0 0 0 A

4-bit Channel ID

or Status Flags

S 7-bit Slave Address R A

Sample A

Clock stretching for conversion time

Sample A + 1

Frame A : Reading ADC data

Frame C : Reading ADC data with status flags or channel ID appended

Frame B : Reading ADC data with averaging enabled

D8 D7 D6AD14D15S 7-bit Slave Address R A D0 A A

4-bit Channel ID

or Status Flags

0 0 0 0

Frame D : Reading ADC data with averaging enabled &

status flags or channel ID appended

Data from host to device Data from device to host

ADS7138

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ZHCSJS8 –MAY 2019

图图 6. Data Frames for Reading Data

When status flags are enabled, APPEND_STATUS is set to 10b and four bits are appended to the ADC output.

The device outputs status flags in this order: {1b, 0b, CRCERR_IN, ALERT}. The level transitions on the digital

interface, resulting from the fixed 1b and 0b in the status flags, can be used to detect if the digital outputs are

shorted to a fixed voltage in the system. The CRCERR_IN flag reflects the corresponding bit in the

GENERAL_CFG register. The ALERT flag is the output of the logical OR of the bits in the EVENT_FLAG

8.3.11 Digital Window Comparator

The internal digital window comparator (DWC) is available in all functional modes of the device (see the Device

Functional Modes section for details). The digital window comparator controls output of the ALERT pin buffer.

The ALERT pin can be configured as open-drain (default) or push-pull output using the ALERT_DRIVE bit in the

ALERT_PIN_CFG register. 图 7 shows a block diagram for the digital window comparator.

图图 7. Digital Window Comparator Block Diagram

ADVANCEINFORMATION

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal above limit

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal below limit

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal out of band

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal in band

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Signal out of band

DWC_CH_POL = 0

DWC_CH_POL = 1

ADS7138

ZHCSJS8 –MAY 2019

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The low-side threshold, high-side threshold, event counter, and hysteresis parameters are independently

programmable for each input channel. 图 8 shows the events that can be monitored for every analog input

channel by the window comparator.

图图 8. Event Monitoring With the Window Comparator

To enable the digital window comparator, set the DWC_EN bit in the GENERAL_CFG register. By default,

hysteresis is 0, the high threshold is 0xFFF, and the low threshold is 0x000. A 12-bit straight binary code cannot

be higher than 0xFFF or lower than 0x000, thus the thresholds have no effect unless set to different values. 图 8

shows the various types of event that can be detected by adjusting the thresholds. For detecting when a signal is

in-band, the EVENT_RGN register must be configured. In each of the cases shown in 图 8, either or both

EVENT_HIGH_FLAG and EVENT_LOW_FLAG can be set.

The programmable event counter counts consecutive thresholds violations before alert flags can be set. The

event count can be set to a higher value to avoid transients in the input signal setting the alert flags.

In order to assert the ALERT pin when the alert flag is set for a particular analog input channel, set the

corresponding bit in the ALERT_CH_SEL register. Alert flags are set regardless of the ALERT_CH_SEL

configuration if DWC_EN is 1 and the high or low thresholds are exceeded.

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