![](https://csdnimg.cn/release/download_crawler_static/87523270/bga.jpg)
D
O
N
O
T
COPY
10 • AR6103 ROCm® Data Sheet Atheros Communications, Inc.
10 • November 2012 PRELIMINARY: ATHEROS CONFIDENTIAL
Delta PWM DAC can provide a continuous
dimmer function.
2.6 MBOX
The MBOX is a service module to handle one of
two possible external hosts: SDIO or GSPI. The
AR6103 can handle only one of these hosts at
any given time. The type of host the AR6103
uses depends upon the polarity of some
package pins upon system power-up. The
MBOX has two interfaces: an APB interface for
access to the MBOX registers and an AHB
interface which is used by the external host to
access the VMC memory or other registers
within the AR6103.
2.7 Debug UART
The AR6103 includes a high-speed Universal
Asynchronous Receiver/Transmitter (UART)
interface that is fully compatible with the 16550
UART industry standard. This UART is a
general purpose UART although it is primarily
used for debug.
2.8 Reset Control
The AR6103 CHIP_PWD_L pin can be used to
completely reset the entire chip. After this
signal has been de-asserted, the AR6103 waits
for host communication. Until then, the MAC,
BB, and SOC blocks are powered off and all
modules except the host interface are held in
reset.
Once the host has initiated communication, the
AR
6103 turns on its crystal and later on its PLL.
After all clocks are stable and running, the
resets to all blocks are automatically de-
asserted. The only resets that stay asserted are
given below:
■
Warm and cold resets to the MAC
■
Warm reset to the radio (The cold reset gets
automatically de-asserted)
The above resets are deasserted by software.
Al
l AR6103 reset control logic resides in the
RTC block to ensure stable reset generation.
2.8.1 CPU Reset
CPU reset is different from the other resets
mentioned above. There are four scenarios
where the CPU reset can be asserted:
1. The AR6103 CHIP_PWD_L pin is asserted
or the host has
not initiated communication.
2. The polarity of certain package pins are set
to enabl
e JTAG debugging via an In-Circuit
Emulator (ICE). In this case, the external
ICE can assert CPU reset through a package
pin.
3. The polarity of a package pin is
set to hold
the CPU in reset until the host clears an
internal AR6103 register.
4. An internal AR6103 register is set by the
host
to force the CPU out of an unknown
state.
2.9 Reset Sequence
After a COLD_RESET event (e.g., the host
toggles CHIP_PWD_L) the AR6103 will enter
the HOST_OFF state and await communication
from the host. From that point, the typical
AR6103 COLD_RESET sequence is shown
below:
1. When the host is ready to use the AR6103, it
i
nitiates communication via SDIO or GSPI.
2. The AR6103 enters the WAKEUP state then
the ON
state and enables the XTENSA CPU
to begin executing ROM code. Software
configures the AR6103 functions and
interfaces. When the AR6103 is ready to
receive commands from the host, it will set
an internal function ready bit.
3. The host reads the ready bit and can now
se
nd function commands to the AR6103.
4. The CPU may continue to be held in reset
under
some circumstances until its reset is
cleared by an external pin or when the host
clears a register.
5. The MAC cold reset and the MAC/BB
warm r
eset will continue to stay asserted
until their respective reset registers are
cleared by software.
2.10 Power Management Unit
The AR6103 has a an integrated Power
Management Unit (PMU) which generates all
the power supplies required by its internal
circuitry from an external battery connection.
The only supplies needed by the AR6103 are
the battery input (4.2V - 3.1V) and the host and
SOC I/O supplies (1.8V - 3.3V).
The main components of the PMU are as
fol
lows:
■
A switching regulator (SWREG) which
produces a 1.8V supply from the battery
input.