ATA/ATAPI-7 V3：2003年发布的串行接口标准与物理连接规范

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"ATA/ATAPI-7, Volume 3 (PDF) 是2003年发布的第七版ATA/ATAPI标准，该标准主要关注于主机系统与存储设备之间的接口规范，旨在为系统制造商、系统集成商、软件供应商以及智能存储设备供应商提供一个通用的连接标准。适用范围包括所有包含存储设备的处理器机箱内的主机系统。此标准由T13委员会（美国电子工业协会信息技术体系结构委员会）制定，作为一项工作草案，其目的是将串行传输协议和物理接口标准化。它定义了在主机和存储设备之间进行通信时使用的电缆、连接器、电气和逻辑信号特性，以及通过接口传输命令、数据和状态的协议。Volume 1主要关注于设备实现标准所需的寄存器交付命令，而Volume 2则侧重于并行接口的相关内容。值得注意的是，尽管这是一个建议性美国国家标准，但它尚未完成，可能根据T10技术委员会在公开审查期间收到的反馈进行修改。用户在使用其中提供的信息时需自行承担风险。成员机构、技术委员会及其关联任务组可在标准化活动中复制此文档，但必须保留所有版权，并且禁止任何商业或盈利性的复制或再发布。 T13技术编辑John Masiewicz来自Western Digital，位于美国加州Lake Forest，他的联系方式供查阅。此外，标准引用了ISO/IEC的国际标准编号和ANSI INCITS的美国国家标准编号，以及印刷日期为四月。 ATA/ATAPI-7 V3是现代计算机硬件架构中的关键组成部分，它确保了不同厂商生产的设备能够无缝地与主机系统集成，从而推动了存储技术的发展和互操作性。"

T13/1532D Volume 3 Revision 4b

Page viii

J.1.13.1

Legacy DMA read from target for odd word count.................................................................................280

J.1.13.2 Legacy DMA write by host to target for odd word count........................................................................281

J.1.13.3 PIO data read from the device.................................................................................................................281

J.1.13.4 PIO data write to the device ....................................................................................................................281

J.1.13.5 First Party DMA read of host memory by device....................................................................................282

J.1.13.6 First Party DMA write of host memory by device ..................................................................................282

Tables

Page

Table 1 − PACKET delivered command sets.....................................................................................................2

Table 2 − 16-bit Transfer Byte order ................................................................................................................14

Table 3 − 8-bit Transfer Byte order ..................................................................................................................14

Table 4 - Device plug connector pin definition .................................................................................................35

Table 5 - Signal integrity requirements and test procedures ...........................................................................41

Table 6 - Housing and contact electrical parameters, test procedures, and requirements .............................46

Table 7 - Mechanical test procedures and requirements.................................................................................47

Table 8 - Environmental parameters, test procedures, and requirements.......................................................48

Table 9 - Additional requirement ......................................................................................................................48

Table 10 - Connector test sequences ..............................................................................................................49

Table 11 - Physical Layer Electrical Requirements..........................................................................................62

Table 12 - Voltage / Timing Margin Definition..................................................................................................69

Table 13 - Sampling differential noise budget..................................................................................................71

Table 14 - Desired peak amplitude reduction by SSC.....................................................................................74

Table 15 − Out of band signal times ................................................................................................................76

Table 16 - Interface power states.....................................................................................................................93

Table 17 - 5b/6b coding..................................................................................................................................106

Table 18 - 3b/4b coding..................................................................................................................................106

Table 19 - Valid data characters ....................................................................................................................108

Table 20 - Valid control characters ................................................................................................................112

Table 21 - Description of primitives................................................................................................................118

Table 22 - Primitive encoding.........................................................................................................................120

Table 23 - Valid CONT Transmission Sequences .........................................................................................121

Table 24 -Latency example............................................................................................................................124

Table 25 - SRST write from host to device transmission breaking through a device to host Data FIS .........125

Table 26 - Shadow Command Block and Shadow Control Block transmission example..............................128

Table 27 - Data from host to device transmission example ...........................................................................129

Table 28 - DMA data from host to device, device terminates transmission example ....................................130

Table 29 - SCR definition ...............................................................................................................................236

Table 30 - SCR Definition...............................................................................................................................236

Table 31 - CRC and scrambler calculation example - PIO Write Command.................................................261

Table 32 - Type field values ...........................................................................................................................262

Figures

Page

Figure 1 − ATA document relationships .............................................................................................................1

Figure 2 − State diagram convention ...............................................................................................................12

Figure 3 - Byte, word and DWORD relationships.............................................................................................15

Figure 4 - Standard ATA device connectivity...................................................................................................17

Figure 5 - The serial implementation of ATA connectivity................................................................................18

Figure 6 - Communication layers .....................................................................................................................19

Figure 7 - Serial implementation connector examples.....................................................................................24

Figure 8 - Device plug connector part 1 of 2....................................................................................................26

Figure 9 - Device Plug Connector part 2 of 2..................................................................................................27

Figure 10 - Non-Latching Signal Cable receptacle connector interface dimensions .......................................28

Figure 11 - Optional Latching Signal Cable Receptacle connector interface dimensions...............................29

Figure 12 - Host plug connector interface dimension ......................................................................................30

T13/1532D Volume 3 Revision 4b

Page ix

Figure 13 - Host receptacle connector interface dimensions........................................................................... 31

Figure 14 - Non-Latching Power receptacle connector interface dimensions ................................................. 33

Figure 15 - Optional Latching Power Cable Receptacle.................................................................................. 34

Figure 16 - Connector pair blind-mate misalignment tolerance....................................................................... 36

Figure 17 - Device-backplane mating configuration ........................................................................................ 36

Figure 18 - Device plug connector location on 3.5” device.............................................................................. 37

Figure 19 - Device plug connector location on 2.5” device.............................................................................. 38

Figure 20 - Recommended host plug spacing for Non-Latching Connectors.................................................. 39

Figure 21 - Recommended host plug connector clearance & Orientation for Optional Latching Connectors. 40

Figure 22 - Signals and grounds assigned in direct connect and cabled ........................................................ 50

Figure 23 - Low transition density pattern........................................................................................................ 52

Figure 24 - Half-rate / quarter-rate high transition density pattern................................................................... 53

Figure 25 - Low frequency spectral content pattern ........................................................................................ 53

Figure 26 - Simultaneous switching outputs patterns...................................................................................... 54

Figure 27- Composite patterns ........................................................................................................................ 54

Figure 28- Compliant test patterns................................................................................................................... 57

Figure 29 - Physical plant overall block diagram ............................................................................................. 59

Figure 30 - Signal rise and fall times................................................................................................................ 66

Figure 31 - Transmit test fixture ...................................................................................................................... 67

Figure 32 - Receive test fixture ........................................................................................................................ 67

Figure 33 - Voltage / timing margin base diagram........................................................................................... 69

Figure 34 - Jitter output/tolerance mask .......................................................................................................... 70

Figure 35 - Jitter measurement example ......................................................................................................... 72

Figure 36 - Triangular frequency modulation profile........................................................................................ 73

Figure 37 - Spectral fundamental frequency comparison................................................................................ 73

Figure 38 - Out of band signals........................................................................................................................ 75

Figure 39 − Host phy initialization state machine (States HP1-HP13) ............................................................ 78

Figure 40 − Device phy initialization state machine (States DP1-DP12)......................................................... 84

Figure 41 - COMRESET sequence.................................................................................................................. 89

Figure 42 - COMINIT sequence....................................................................................................................... 91

Figure 43 - Power-on Sequence...................................................................................................................... 94

Figure 44 - On to Partial/Slumber - host initiated............................................................................................. 95

Figure 45 - ON to Partial/Slumber - device initiated ........................................................................................ 97

Figure 46 - Loopback far-end retimed............................................................................................................. 99

Figure 47 - Loopback far-end analog........................................................................................................... 100

Figure 48 - Loopback - near-end analog........................................................................................................ 101

Figure 49 - Bit designations ........................................................................................................................... 103

Figure 50 - Nomenclature reference.............................................................................................................. 103

Figure 51 - Conversion examples.................................................................................................................. 104

Figure 52 - Coding examples......................................................................................................................... 107

Figure 53 - Bit ordering and significance ....................................................................................................... 113

Figure 54 - Single bit error with two character delay ..................................................................................... 115

Figure 55 - Single bit error with one character delay..................................................................................... 115

Figure 56 - Transmission structures .............................................................................................................. 116

Figure 57 - CONT usage example ................................................................................................................. 127

Figure 58 − Link idle state diagram (States L1, LS1-LS3)............................................................................. 133

Figure 59 − Link transmit state diagram (States LT1-LT9) ............................................................................ 136

Figure 60 − Link receive state diagram (States LR1-LR9)............................................................................. 142

Figure 61 − Link power mode state diagram (States LPM1-LPM8)............................................................... 147

Figure 62 - Register - Host to Device FIS layout ........................................................................................... 152

Figure 63 - Register - Device to Host FIS layout ........................................................................................... 154

Figure 64 - Set Device Bit - Device to Host FIS layout.................................................................................. 156

Figure 65 - DMA Activate - Device to Host FIS layout................................................................................... 158

Figure 66 - First Party DMA Setup - Device to Host FIS layout..................................................................... 159

Figure 67 - BIST Activate - Bidirectional........................................................................................................ 161

Figure 68 - PIO Setup - Device to Host FIS layout ........................................................................................ 163

Figure 69 - Data - Host to Device or Device to Host FIS layout .................................................................... 165

Figure 70 − Host transport idle state diagram (States HTI1-HTI2) ................................................................ 167

T13/1532D Volume 3 Revision 4b

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Figure 71 − Host transport transmit command FIS diagram (States HTCM1-HTCM2) .................................170

Figure 72 − Host transport transmit control FIS diagram (States HTCR1-HTCR2).......................................172

Figure 73 − Host transport transmit First Party DMA setup - device to host or host to device FIS (States

HTDMASTUP0-HTDMASTUP1).............................................................................................................173

Figure 74 − Host transport transmit BIST activate FIS (States HTXBIST0-HTXBIST1)................................175

Figure 75 - Host transport decompose register FIS diagram (States HTR1- HTR2).....................................176

Figure 76 − Host transport decompose Set Device Bits FIS state diagram (States HTDB0-HTDB1)...........177

Figure 77 − Host transport decompose DMA activate FIS diagram (States HTDA1-HTDA5).......................178

Figure 78 − Host transport decompose PIO setup FIS state diagram (States HTPS1-HTPS6)....................181

Figure 79 − Host transport decompose First Party DMA Setup FIS state diagram (State HTDS1) ..............184

Figure 80 − Host transport decompose BIST activate FIS state diagram (State HTRBIST0-HTRBIST1).....185

Figure 81 − Device transport idle state diagram (States DTI0-DTI1).............................................................186

Figure 82 − Device transport send register - Device to host state diagram (DTR0-DTR1) ...........................188

Figure 83 − Device transport send set device bits FIS state diagram (DTDB0-DTDB1) ...............................189

Figure 84 − Device transport transmit PIO setup - device to host FIS state diagram (States DTPIOSTUP0-

DTPIOSTUP1) ........................................................................................................................................190

Figure 85 − Device transport transmit DMA activate FIS state diagram (States DTDMAACT0-DTDMAACT1)

................................................................................................................................................................191

Figure 86 − Device transport transmit First Party DMA setup - device to host state diagram (States

DTDMASTUP0-DTDMASTUP1).............................................................................................................192

Figure 87 − Device transport transmit data - device to host FIS diagram (State DTDATAI0-DTDATAI2).....193

Figure 88 − Device transport transmit BIST activate FIS diagram (States DTXBIST0-DTXBIST1) ..............195

Figure 89 − Device transport decompose register - host to device state diagram (State DTCMD0).............196

Figure 90 − Device transport decompose data (host to device) FIS state diagram (States DTDATAO0-

DTDATAO2)............................................................................................................................................197

Figure 91 − Device transport decompose First Party DMA Setup FIS - host to device or device to host state

diagram (State DTDMASTUP0)..............................................................................................................199

Figure 92 - Device transport decompose BIST activate FIS (States (DTRBIST0-DTRBIST1)......................200

Figure 93 - Power on and COMRESET protocol (States DHR0-DHR3)........................................................202

Figure 94 - Device idle protocol (States DI0-DI7) ..........................................................................................204

Figure 95 - Software reset protocol (States DSR0-DSR3).............................................................................208

Figure 96 - EXECUTE DEVICE DIAGNOSTIC command protocol (States DEDD0-DEDD2).......................210

Figure 97 - DEVICE RESET command protocol (States DDR0-DDR1) ........................................................211

Figure 98 - Non-data command protocol (States DND0-DND1)....................................................................212

Figure 99 - PIO data-in command protocol (States DPIOI0-DPIOI3) ............................................................213

Figure 100 - PIO data-out command protocol (States DPIOO0-DPIOO3) ....................................................215

Figure 101 - DMA data-in command protocol (States DDMAI0-DDMAI1).....................................................217

Figure 102 - DMA data-out command protocol (States DDMAO0-DDMAO3)...............................................219

Figure 103 - PACKET command protocol (States DP0-DP16)......................................................................221

Figure 104 - READ DMA QUEUED command protocol (States DDMAQI0-DDMAQI4)................................226

Figure 105 - WRITE DMA QUEUED command protocol (DDMAOQ0-DDMAQO5)......................................228

Figure 106 − Host adapter state diagram (States HA0-HA2).........................................................................231

Figure 107 - Error handling architecture ........................................................................................................241

Figure 108 - Cable construction example ......................................................................................................263

Figure 109 - Jitter as a function of frequency.................................................................................................265

Figure 110 - Sampling bit error rate formulas ................................................................................................266

Figure 111 - Transmitter examples ................................................................................................................267

Figure 112 - OOB signal detector ..................................................................................................................269

Figure 113 - Squelch detector........................................................................................................................270