5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D18
DDR_A_D19
DDR_A_D21
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D45
DDR_A_D46
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
DDR_A_MA3
DDR_A_MA4DDR_A_MA5
DDR_A_MA6DDR_A_MA8
DDR_A_MA7DDR_A_MA9
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
M_ODT0
M_ODT1
DDR_A_D63
DDR_A_MA15
DDR_A_D23
DDR_A_D31
DDR_A_D17
DDR_A_D9 DDR_A_D13
DDR_A_D20DDR_A_D16
DDR_A_D25
DDR_A_D30
DDR_A_D24
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A_D39
DDR_A_D54
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D48
DDR3_DRAMRST#_R
DDR3_DRAMRST#_R
+0.75V_DDR_VTT
+1.5V_MEM
+1.5V_MEM+1.5V_MEM
+3.3V_RUN
+0.75V_DDR_VTT+0.75V_DDR_VTT
+1.5V_MEM
+1.5V_MEM
+DIMM0_1_VREF_DQ
+DIMM0_1_VREF_CA
+DIMM0_1_CA_CPU
+V_DDR_REF
+V_DDR_REF
+DIMM0_1_VREF_CPU
DDR_A_D[0..63]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..15]8
DDR_A_DQS#[0..7]8
DDR_CKE0_DIMMA8
DDR_A_BS28
DDR_CS1_DIMMA#8
DDR_A_WE#8
DDR_A_CAS#8
DDR_A_BS08
DDR_A_BS1 8
M_ODT0 8
DDR_A_RAS# 8
M_CLK_DDR1 8
M_CLK_DDR#1 8M_CLK_DDR#08
M_CLK_DDR08
DDR_XDP_WAN_SMBCLK 13,15,28,37
DDR_CKE1_DIMMA 8
DDR_CS0_DIMMA# 8
M_ODT1 8
DDR3_DRAMRST# 7DDR3_DRAMRST#_R13
DDR_XDP_WAN_SMBDAT 13,15,28,37
Title
Size Document Number Rev
Date: Sheet of
LA-6611P
0.3
DDRIII-SODIMM SLOT1
12 64Wednesday, January 26, 2011
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-6611P
0.3
DDRIII-SODIMM SLOT1
12 64Wednesday, January 26, 2011
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-6611P
0.3
DDRIII-SODIMM SLOT1
12 64Wednesday, January 26, 2011
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DIMMA H=4.0mm
2-3A to 1 DIMMs/channel
Link Done
All VREF traces should
have 10 mil trace width
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMMA
Layout Note:
Place near JDIMMA.203,204
Populate RD1 for Intel DDR3
VREFDQ multiple methods M1
CD3
1U_0402_6.3V6K~D
CD3
1U_0402_6.3V6K~D
1
2
RD7 0_0402_5%~D@RD7 0_0402_5%~D@
1 2
CD6
1U_0402_6.3V6K~D
CD6
1U_0402_6.3V6K~D
1
2
CD11
10U_0603_6.3V6M~D
CD11
10U_0603_6.3V6M~D
1
2
CD7
10U_0603_6.3V6M~D
CD7
10U_0603_6.3V6M~D
1
2
CD22
2.2U_0603_6.3V6K~D
CD22
2.2U_0603_6.3V6K~D
1
2
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
CD13
10U_0603_6.3V6M~D
@CD13
10U_0603_6.3V6M~D
@
1
2
CD5
1U_0402_6.3V6K~D
CD5
1U_0402_6.3V6K~D
1
2
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
1 2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
1 2
CD10
10U_0603_6.3V6M~D
CD10
10U_0603_6.3V6M~D
1
2
RD310_0402_5%~D @RD310_0402_5%~D @
12
CD15
2.2U_0603_6.3V6K~D
CD15
2.2U_0603_6.3V6K~D
1
2
CD8
10U_0603_6.3V6M~D
CD8
10U_0603_6.3V6M~D
1
2
JDIMMA1
TYCO_2-2013022-2~D
CONN@JDIMMA1
TYCO_2-2013022-2~D
CONN@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS
2
DQ4
4
DQ5
6
VSS
8
DQS0#
10
DQS0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
RESET#
30
VSS
32
DQ14
34
DQ15
36
VSS
38
DQ20
40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21
42
VSS
44
DM2
46
VSS
48
DQ22
50
DQ23
52
VSS
54
DQ28
56
DQ29
58
VSS
60
DQS3#
62
DQS3
64
VSS
66
DQ30
68
DQ31
70
VSS
72
CKE1
74
VDD
76
A15
78
A14
80
VDD
82
A11
84
A7
86
VDD
88
A6
90
A4
92
VDD
94
A2
96
A0
98
VDD
100
CK1
102
CK1#
104
VDD
106
BA1
108
RAS#
110
VDD
112
S0#
114
ODT0
116
VDD
118
ODT1
120
NC
122
VDD
124
VREF_CA
126
VSS
128
DQ36
130
DQ37
132
VSS
134
DM4
136
VSS
138
DQ38
140
DQ39
142
VSS
144
DQ44
146
DQ45
148
VSS
150
DQS5#
152
DQS5
154
VSS
156
DQ46
158
DQ47
160
VSS
162
DQ52
164
DQ53
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
EVENT#
198
SDA
200
SA1
201
VTT
203
GND1
205
SCL
202
VTT
204
GND1
206
CD17
1U_0402_6.3V6K~D
CD17
1U_0402_6.3V6K~D
1
2
CD2
0.1U_0402_16V4Z~D
CD2
0.1U_0402_16V4Z~D
1
2
CD16
0.1U_0402_16V4Z~D
CD16
0.1U_0402_16V4Z~D
1
2
RD290_0402_5%~D RD290_0402_5%~D
12
CD9
10U_0603_6.3V6M~D
CD9
10U_0603_6.3V6M~D
1
2
+
CD14
330U_SX_2VY~D
+
CD14
330U_SX_2VY~D
1
2
CD21
0.1U_0402_16V4Z~D
CD21
0.1U_0402_16V4Z~D
1
2
CD18
1U_0402_6.3V6K~D
CD18
1U_0402_6.3V6K~D
1
2
CD20
1U_0402_6.3V6K~D
CD20
1U_0402_6.3V6K~D
1
2
CD12
10U_0603_6.3V6M~D
CD12
10U_0603_6.3V6M~D
1
2
CD1
2.2U_0603_6.3V6K~D
CD1
2.2U_0603_6.3V6K~D
1
2
CD4
1U_0402_6.3V6K~D
CD4
1U_0402_6.3V6K~D
1
2
RD27
1K_0402_1%~D
RD27
1K_0402_1%~D
12
CD19
1U_0402_6.3V6K~D
CD19
1U_0402_6.3V6K~D
1
2
RD1 0_0402_5%~DRD1 0_0402_5%~D
1 2