"基于51单片机的数字频率合成设计与实现"

The graduation thesis "Frequency Synthesis Design Based on 51 Single Chip Microcomputer" is a comprehensive study on the design and implementation of a frequency synthesis system. The system is centered around the 51 single chip microcomputer and includes modules for sine signal generation, power amplification, amplitude modulation (AM), frequency modulation (FM), digital key control (ASK, PSK), and test signal generation. The system utilizes digital control to generate sine signals in the range of 0Hz to 30MHz using a DDS chip AD9850. The generated signal is then amplified and filtered to a 6V output with a certain driving capability. Additionally, the system is capable of modulating the 1kHz sine signal generated by the test signal module through AM and FM modules, as well as producing binary PSK or ASK signals through the digital key control module. It also includes the functionality for demodulating ASK signals to recover the original digital sequence. The system aims for simplicity, easy adjustment, and comprehensive functionality, and has achieved stable waveform output and high accuracy. It also features an LED display screen and keyboard to provide a user-friendly human-machine interface. The key technologies and components involved in the system are direct digital frequency synthesis (DDS), AD9850, phase-locked loop (PLL), and voltage-controlled oscillator (VCO). This thesis presents a detailed exploration of the system’s design, performance, and practical application. Overall, the system represents a significant accomplishment in the field of frequency synthesis and digital signal processing. Keywords: direct digital frequency synthesis (DDS), AD9850, phase-locked loop (PLL), VCO, amplitude modulation (AM), frequency modulation (FM), digital key control (ASK, PSK).