Cypress CY14B064I-SFXI: 64-Kbit Serial nvSRAM with Real-Time Clock

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"CYPRESS-CY14B064I-SFXI.pdf" 是 Cypress Semiconductor Corporation 提供的一种64-Kbit (8K×8) Serial (I2C) 非易失性静态随机存取存储器(nvSRAM)的数据手册，该器件集成有实时时钟(RTC)功能。 CY14C064I、CY14B064I 和 CY14E064I 是同一系列的不同型号，它们提供64千比特的非易失性存储空间，内部结构为8K字节乘以8位。这种nvSRAM的主要特点包括： 1. 自动化存储机制：在电源下降时（AutoStore）或通过I2C命令（Software STORE）或高电平存储引脚（Hardware STORE）触发STORE操作，将数据安全地保存在量子陷阱非易失性元素中。 2. 电源上电时的自动召回（Power-Up RECALL）：在电源恢复时，或者通过I2C命令（Software RECALL）执行数据到SRAM的召回。 3. 高可靠性：无限次的读、写和召回操作循环，保证了设备的耐用性。量子陷阱可承受至少1百万次的STORE周期，并且在85°C的温度下，数据保留能力长达20年。 4. 实时时钟功能（RTC）：具备完整的RTC功能，包括看门狗定时器、可编程中断的时钟报警、备用电源故障指示、可编程频率的方波输出（1Hz、512Hz、4096Hz、32.768kHz）。RTC支持电容器或电池备份，备份电流仅为0.45微安（典型值）。这些特性使CY14B064I系列适用于需要在断电后保持数据和时间信息的应用，如工业控制、仪表设备、家用电器、网络设备和任何需要保持状态和时间记录的系统。其I2C接口使其易于与微控制器集成，减少了外部组件的需求，降低了系统成本。此外，低功耗设计对于电池供电或能量采集应用尤为有利。在设计时，工程师应考虑器件的电气参数、工作电压范围以及与微控制器或其他系统的兼容性，确保系统的稳定运行。

Document Number: 001-68169 Rev. *J Page 8 of 42

CY14C064I

CY14B064I

CY14E064I

Memory Control Register

The Memory Control Register contains the following bits:

■ BP1:BP0: Block protect bits are used to protect 1/4, 1/2 or full

memory array. These bits can be written through a write

instruction to the 0x00 location of the Control Register Slave

device. However, any STORE cycle transfers SRAM data into

a nonvolatile cell regardless of whether or not the block is

protected. The default value shipped from the factory for BP0

and BP1 is ‘0’.

■ S/N Lock (SNL) Bit: Serial Number Lock bit (SNL) is used to

lock the serial number. After the bit is set to ‘1’, the serial number

registers are locked and no modification is allowed. This bit

cannot be cleared to ‘0’. The serial number is secured on the

next STORE operation (Software STORE or AutoStore). If

AutoStore is not enabled, user must perform the Software

STORE operation to secure the lock bit status. If a STORE was

not performed, the serial number lock bit will not survive the

power cycle. The default value shipped from the factory for SNL

is ‘0’.

Command Register

The Command Register resides at address ‘AA’ of the Control

Registers Slave device. This is a write only register. The byte

written to this register initiates a STORE, RECALL, AutoStore

Enable, AutoStore Disable, and Sleep mode operation as listed

in Table 5. The section Executing Commands Using Command

■ STORE: Initiates nvSRAM Software STORE. The nvSRAM

cannot be accessed for t

STORE

time after this instruction has

been executed. When initiated, the device performs a STORE

operation regardless of whether or not a write has been

performed since the last NV operation. After the t

STORE

cycle

time is completed, the SRAM is activated again for read/write

operations.

■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM

cannot be accessed for t

RECALL

time after this instruction has

been executed. The RECALL operation does not alter the data

in the nonvolatile elements. A RECALL may be initiated in two

ways: Hardware RECALL, initiated on power-up; and Software

RECALL, initiated by a I

C RECALL instruction.

■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be

accessed for t

time after this instruction has been executed.

This setting is not nonvolatile and needs to be followed by a

manual STORE sequence if this is desired to survive the power

cycle. The part comes from the factory with AutoStore Enabled

and 0x00 written in all cells.

■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot

be accessed for t

time after this instruction has been

executed. This setting is not nonvolatile and needs to be

followed by a manual STORE sequence if this is desired to

survive the power cycle.

Note If AutoStore is disabled and V

CAP

is not required, it is

required that the V

CAP

pin is left open. V

CAP

pin must never be

Figure 9. Control Registers Slave Device Address

Table 2. Control Registers Map

Address Description Read/Write Details

0x00 Memory

Control

Read/Write Contains Block

Protect bits and Serial

Number lock bit

0x01 Serial Number

8 bytes

Read/Write

(Read only

when SNL

is set)

Programmable Serial

Number. Locked by

setting the Serial

Number lock bit in the

Memory Control

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09 Device ID Read only Device ID is factory

programmed

0x0A

0x0B

0x0C

0x0D Reserved Reserved Reserved

0xAA Command

Write only Allows commands for

STORE, RECALL,

AutoStore

Enable/Disable,

SLEEP Mode

Table 3. Memory Control Register Bits

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0SNL

(0)

0 0 BP1

(0)

BP0

(0)

Table 4. Block Protection

Level BP1:BP0 Block Protection

0 00 None

1/4 01

0x1800–0x1FFF

1/2 10

0x1000–0x1FFF

111

0x0000–0x1FFF

handbook, halfpage

R/W

LSBMSB

Slave ID

A2 A0A1

Device Select

Table 5. Command Register Bytes

Data Byte

[7:0]

Command Description

0011 1100 STORE STORE SRAM data to nonvolatile

memory

0110 0000 RECALL RECALL data from nonvolatile

memory to SRAM

0101 1001 ASENB Enable AutoStore

0001 1001 ASDISB Disable AutoStore

1011 1001 SLEEP Enter Sleep Mode for low power

consumption

Document Number: 001-68169 Rev. *J Page 9 of 42

CY14C064I

CY14B064I

CY14E064I

connected to ground. Power Up RECALL operation cannot be

disabled in any case.

■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.

When the SLEEP instruction is registered, the nvSRAM takes

time to process the SLEEP request. Once the SLEEP

command is successfully registered and processed, the

nvSRAM toggles HSB LOW, performs a STORE operation to

secure the data to nonvolatile memory and then enters into

SLEEP mode. Whenever nvSRAM enters into sleep mode, it

initiates non volatile STORE cycle which results in losing an

endurance cycle per sleep command execution. A STORE

cycle starts only if a write to the SRAM has been performed

since the last STORE or RECALL cycle.

The nvSRAM enters into sleep mode in this manner:

1. The master sends a START command.

2. The master sends Control Registers Slave device ID with I

write bit set (R/W

= ’0’).

3. The slave (nvSRAM) sends an ACK back to the master.

4. The master sends Command Register address (0xAA).

5. The slave (nvSRAM) sends an ACK back to the master.

6. The master sends Command Register byte for entering into

sleep mode.

7. The slave (nvSRAM) sends an ACK back to the master.

8. The master generates a STOP condition.

Once in sleep mode, the device starts consuming I

current

SLEEP

time after SLEEP instruction is registered. The device is

not accessible for normal operations until it is out of sleep mode.

The nvSRAM wakes up after t

WAKE

duration after the device

slave address is transmitted by the master.

Transmitting any of the three slave addresses wakes the

nvSRAM from sleep mode. The nvSRAM device is not

accessible during t

SLEEP

and t

WAKE

interval and any attempt to

access the nvSRAM device by the master is ignored and

nvSRAM sends NACK to the master. An alternate method of

determining when the device is ready is for the master can send

read or write commands and look for an ACK.

Write Protection (WP)

The Write Protect (WP) pin is an active HIGH pin and protects

the entire memory and all registers from write operations. To

inhibit all the write operations, this pin must be held HIGH. When

this pin is HIGH, all memory and register writes are prohibited

and the address counter is not incremented. This pin is internally

pulled LOW and, therefore, can be left open if not used.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM that

automatically stores the SRAM data to QuantumTrap cells

during power-down. This STORE makes use of an external

capacitor (V

CAP

) and enables the device to safely STORE the

data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from V

charge the capacitor connected to the V

CAP

pin. When the

voltage on the V

pin drops below V

SWITCH

during power-down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a conditional STORE operation using the

charge from the V

CAP

capacitor. The AutoStore operation is not

initiated if no write cycle has been performed since the last

STORE or RECALL.

Note If a capacitor is not connected to V

CAP

pin, AutoStore must

be disabled by issuing the AutoStore Disable instruction

specified in Command Register on page 8. If AutoStore is

enabled without a capacitor on V

CAP

pin, the device attempts an

AutoStore operation without sufficient charge to complete the

Store. This will corrupt the data stored in nvSRAM as well as the

serial number and it will unlock the SNL bit.

Figure 10 shows the proper connection of the storage capacitor

CAP

) for AutoStore operation. See the DC Electrical

Characteristics on page 30 for the size of the V

CAP

Figure 10. AutoStore Mode

Hardware STORE and HSB pin Operation

The HSB pin in CY14X064I is used to control and acknowledge

STORE operations. If no STORE or RECALL is in progress, this

pin can be used to request a Hardware STORE cycle. When the

HSB

pin is driven LOW, the device conditionally initiates a

STORE operation after t

DELAY

duration. An actual STORE cycle

starts only if a write to the SRAM has been performed since the

last STORE or RECALL cycle. Reads and Writes to the memory

are inhibited for t

STORE

duration or as long as HSB pin is LOW.

The HSB pin also acts as an open drain driver (internal 100 k

weak pull-up resistor) that is internally driven LOW to indicate a

busy condition when the STORE (initiated by any means) is in

progress.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (t

HHHD

) with standard output high

current and then remains HIGH by internal 100 k pull-up

resistor.

Note For successful last data byte STORE, a hardware STORE

should be initiated at least one clock cycle after the last data bit

D0 is received.

Upon completion of the STORE operation, the nvSRAM memory

access is inhibited for t

LZHSB

time after HSB pin returns HIGH.

Leave the HSB

pin unconnected if not used.

Hardware RECALL (Power Up)

During power-up, when V

crosses V

SWITCH

, an automatic

RECALL sequence is initiated that transfers the content of

nonvolatile memory to the SRAM. The data may have been

0.1 uF

CAP

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