Hi3751 V510 Brief Data Sheet
Copyright © HiSilicon(shanghai) Technologies Co., Ltd. 2019. All rights reserved.
Zone D, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China
Postal Code: 518129 1 www.hisilicon.com
Issue: 02 Date: 2019-05-08
Key Specifications
Key Features
64-bit CPU
DTMB meeting new international performance
requirements
Embedded HDMI 2.0
Comprehensive integrated digital television solution
Security processing feature
High-Performance CPU
64-bit dual-core RISC
Maximum frequency of 1.2 GHz, supporting intelligent
applications smoothly
Independent I-cache, D-cache, and L2 cache
Integrated multimedia acceleration engine NEON
Integrated hardware floating-point coprocessor
TS Demultiplexing/PVR
A maximum of 96 hardware PID channels
Full-service PVR
Recording of scrambled and non-scrambled streams
Video Decoding
HEVC (H.265) MP@level 5.0 high-tier, 4K x 2K@30 fps
H.264 BP/MP/HP@level 5.0, 4K x 2K@30 fps
MVC, 1080p@60 fps
MPEG1, 1080p@60 fps
MPEG2 SP@ML, MP@HL, and 1080p@60 fps
MPEG4 SP@level 0−3, ASP@level 0−5, GMC, 1080p@60
fps
MPEG4 short header format (H.263 baseline), 1080p@60
fps
AVS baseline@level 6.0, AVS+(AVS-P16), and 1080p@60
fps
VC-1 SP@ML, MP@HL, and AP@level 0−3, 1080p@60
fps
VP6/8, 1080p@60 fps
Low-delay decoding
Multi-channel decoding
Image Decoding
JPEG hardware decoding, a maximum of 64 megapixels
Supported formats of 400, 420, 411, 422, 422T, and 444
MJPEG baseline decoding
PNG hardware decoding, maximum 64 megapixels
Gray-scale image, true color image, indexed-color image,
gray-scale image with alpha channel data, and true color
image with alpha channel data
Video Encoding
H.264 BP/MP@level 4.2 video encoding, 1x720p@30 fps
encoding
1/4 pixel motion estimation, CABAC encoding
Low-delay encoding
Encoding of multiple ROIs
VBR and CBR modes
2D Graphics Acceleration
Hardware acceleration engine, supporting highly efficient
2D processing
Data formats of ARGB, CLUT, and AYCbCr
Copying, filling, pattern filling, resizing, clipping, alpha
blending, colorkey, and clip mask
ROP
Anti-flicker, gamma correction, and contrast/luminance
adjustment
Programmable scanning mode
Linked-list operation
3D GPU
Quad-core high-performance GPU
1080p graphics rendering
OpenGL ES 2.0/1.1/1.0 and OpenVG 1.1
Intermediate-Frequency Demodulation for
Analog TV
All analog TV standards, including M/N, B/G/H, D/K, I, L,
and L'
Tuner low- and intermediate-frequency inputs and
configurable intermediate frequency
External SAW not required
Group delay compensation and equalization filter
Digital Demodulation
Tuner low- and intermediate-frequency inputs and
embedded 12-bit ADC
One embedded DVB-C QAM demodulator
− ITU-T J.83 Annex A/B/C
− DVB-C 0.7−7 Mbaud symbol rate and correctable carrier
frequency deviation range ±700 kHz
One embedded DVB-T demodulator
− Standard version 1.51
− Low- and intermediate-frequency and high- and
intermediate-frequency (36 MHz) inputs
− Rapid signal acquisition (less than 200 ms), reducing
the wait time for switching the channel
− Adaptive spectrum reverse recognition
− Frequency error detecting range broader than [–600 kHz,
+600 kHz]
− Compliant with various test standards, including DTG7.0,
NorDig-Unified Test Specification V2.2.1, and Digital
Europe Ebook
One embedded DTMB demodulator
− All 330 clock modes of the standard DTMB
(GB20600-2006)
− 6 MHz, 7 MHz, and 8 MHz input bandwidth
− Low- and intermediate-frequency (4−11 MHz) and high-