使用Vivado HLS进行FPGA设计入门

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"ug998-vivado-intro-fpga-design-hls.pdf" 是一份介绍使用Vivado高层面综合（HLS）进行FPGA设计的文档，版本为v1.1，发布日期为2019年1月22日。这份文档主要面向软件工程师，帮助他们理解如何将软件模型或原型转换为适合不同硬件平台的实施项目，特别是FPGA（现场可编程门阵列）。 FPGA设计与Vivado HLS Vivado HLS是一种工具，它允许软件工程师以高级语言（如C、C++或SystemC）编写设计，并自动将其转换为硬件描述语言（如VHDL或Verilog），进一步用于FPGA的配置。这种技术称为高层面综合，它简化了传统硬件描述语言的复杂性，使得设计过程更加接近软件开发的流程。文档的修订历史文档的最新版本1.1在2019年1月22日发布，包含了编辑性的更新以及对DSP块的更新信息，新增了关于UltraRAM的内容。初版则在2013年7月2日发布。主要内容概述 1. **介绍**：这部分提供了一个概述，解释了FPGA设计的基本概念，以及为什么软件工程师会考虑使用Vivado HLS。 2. **什么是FPGA？**：这部分深入介绍了FPGA的架构，强调其并行处理能力与处理器架构的区别。 3. **硬件设计基础**：讨论了时钟频率、延迟和流水线、吞吐量以及内存架构和布局等关键硬件设计概念。 4. **Vivado HLS基础**：涵盖了Vivado HLS支持的操作，如条件语句、循环、函数以及动态内存分配等。通过学习这份文档，读者可以了解到如何利用Vivado HLS来创建高效能的FPGA设计，以及如何利用软件工程的思维来优化硬件实现。这包括了理解如何处理控制流、数据流以及内存管理，这些都是在设计FPGA系统时至关重要的因素。同时，文档还介绍了FPGA架构的优势，例如其高度可配置性和并行处理能力，这些都是传统处理器无法比拟的。在实际应用中，FPGA设计能够满足高性能、低延迟和定制化的需求，特别是在通信、娱乐、游戏和医疗等领域。通过Vivado HLS，软件工程师能够更快速地将软件原型转化为适用于FPGA的硬件实现，从而加速产品上市时间。

Introduction to FPGA Design with Vivado HLS 15

UG998 (v1.1) January 22, 2019 www.xilinx.com

Chapter 2: What is an FPGA?

Flip-Flop

The flip-flop is the basic storage unit within the FPGA fabric. This element is always paired

with a LUT to assist in logic pipelining and data storage. The basic structure of a flip-flop

includes a data input, clock input, clock enable, reset, and data output. During normal

operation, any value at the data input port is latched and passed to the output on every

pulse of the clock. The purpose of the clock enable pin is to allow the flip-flop to hold a

specific value for more than one clock pulse. New data inputs are only latched and passed

to the data output port when both clock and clock enable are equal to one. Figure 2-4

shows the structure of a flip-flop.

X-Ref Target - Figure 2-4

Figure 2-4: Structure of a Flip-Flop

d_in

d_out

clk_en

clk

reset

set

X13470

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Introduction to FPGA Design with Vivado HLS 17

UG998 (v1.1) January 22, 2019 www.xilinx.com

Chapter 2: What is an FPGA?

configuration, the data can be read and written at any time during the runtime of the

circuit. In contrast, in a ROM configuration, data can only be read during the runtime of the

circuit. The data of the ROM is written as part of the FPGA configuration and cannot be

modified in any way.

The UltraRAM blocks are dual-port, synchronous 288 Kb RAM with a fixed configuration of

4,096 bits deep and 72 bits wide. They are available on UltraScale+ Devices and provide 8

times more storage capacity than the BRAM.

As previously discussed, the LUT is a small memory in which the contents of a truth table are

written during device configuration. Due to the flexibility of the LUT structure in Xilinx

FPGAs, these blocks can be used as 64-bit memories and are commonly referred to as

distributed memories. This is the fastest kind of memory available on the FPGA device,

because it can be instantiated in any part of the fabric that improves the performance of the

implemented circuit.

The shift register is a chain of registers connected to each other. The purpose of this

structure is to provide data reuse along a computational path, such as with a filter. For

example, a basic filter is composed of a chain of multipliers that multiply a data sample

against a set of coefficients. By using a shift register to store the input data, a built-in data

transport structure moves the data sample to the next multiplier in the chain on every clock

cycle. Figure 2-6 shows an example shift register.

FPGA Parallelism Versus Processor Architectures

When compared with processor architectures, the structures that comprise the FPGA fabric

enable a high degree of parallelism in application execution. The custom processing

architecture generated by the Vivado HLS compiler for a software program presents a

different execution paradigm, which must be taken into account when deciding to port an

application from a processor to an FPGA. To examine the benefits of the FPGA execution

paradigm, this section provides a brief review of processor program execution.

X-Ref Target - Figure 2-6

Figure 2-6: Structure of an Addressable Shift Register

A[4:0]

00000 11111

00110

X13471

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Introduction to FPGA Design with Vivado HLS 18

UG998 (v1.1) January 22, 2019 www.xilinx.com

Chapter 2: What is an FPGA?

Program Execution on a Processor

A processor, regardless of its type, executes a program as a sequence of instructions that

translate into useful computations for the software application. This sequence of

instructions is generated by processor compiler tools, such as the GNU Compiler Collection

(GCC), which transform an algorithm expressed in C/C++ into assembly language

constructs that are native to the processor. The job of a processor compiler is to take a C

function of the form:

Equation 2-5

and transform it into assembly code as follows:

The assembly code in Figure 2-7 defines the addition operation to compute the value of z

in terms of the internal registers of a processor. The code states that the input values for the

computation are stored in registers R1 and R2, and the result of the computation is stored

in register R3. This code is simple, and it does not express all the instructions needed to

compute the value of z. This code only handles the computation after the data has arrived

at the processor. Therefore, the compiler must create additional assembly language

instructions to load the registers of the processor with data from a central memory and to

write back the result to memory. The complete assembly program to compute the value of

z is as follows:

The code in Figure 2-8 shows that even a simple operation, such as the addition of two

values, results in multiple assembly instructions. The computational latency of each

instruction is not equal across instruction types. For example, depending on the location of

a and b, the LD operations take a different number of clock cycles to complete. If the values

are in the processor cache, these load operations complete within a few tens of clock cycles.

If the values are in the main, double data rate (DDR) memory, the operations take between

hundreds and thousands of clock cycles to complete. If the values are in a hard drive, the

load operations take even longer to complete. This is why software engineers with cache hit

traces spend so much time restructuring their algorithms to increase the spatial locality of

data in memory to increase the cache hit rate and decrease the processor time spent per

instruction.

X-Ref Target - Figure 2-7

Figure 2-7: Computation Expressed Assembly Code

X-Ref Target - Figure 2-8

Figure 2-8: Complete Assembly Program to Compute Z

zab;+=

ADD $R1,$R2,$R3

LD a, $R1

LD b, $R2

ADD $R1,$R2,$R3

ST $R3, c

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Introduction to FPGA Design with Vivado HLS 19

UG998 (v1.1) January 22, 2019 www.xilinx.com

Chapter 2: What is an FPGA?

IMPORTANT: The level of effort required by the software engineer in restructuring algorithms to better

fit the available processor cache is not required when the same operation is implemented in an FPGA.

Program Execution on an FPGA

The FPGA is an inherently parallel processing fabric capable of implementing any logical

and arithmetic function that can run on a processor. The main difference is that the Vivado

HLS compiler, which is used to transform software descriptions into RTL, is not hindered by

the restrictions of a cache and a unified memory space.

The computation of z is compiled by Vivado HLS into several LUTs required to achieve the

size of the output operand. For example, assume that in the original software program the

variable a, b, and z are defined with the short data type. This type, which defines a 16-bit

data container, gets implemented as 16 LUTs by Vivado HLS.

Note:

As a general rule, 1 LUT is equivalent to 1 bit of computation.

The LUTs used for the computation of z are exclusive to this operation only. Unlike a

processor, where all computations share the same ALU, an FPGA implementation

instantiates independent sets of LUTs for each computation in the software algorithm.

In addition to assigning unique LUT resources per computation, the FPGA differs from a

processor in both memory architecture and the cost of memory accesses. In an FPGA

implementation, the Vivado HLS compiler arranges memories into multiple storage banks

as close as possible to the point of use in the operation. This results in an instantaneous

memory bandwidth, which far exceeds the capabilities of a processor. For example, the

Xilinx Kintex®-7 410T device has a total of 1,590 18 k-bit BRAMs available. In terms of

memory bandwidth, the memory layout of this device provides the software engineer with

the capacity of 0.5M-bits per second at the register level and 23T-bits per second at the

BRAM level.

With regard to computational throughput and memory bandwidth, the Vivado HLS

compiler exercises the capabilities of the FPGA fabric through the processes of scheduling,

pipelining, and dataflow. Although transparent to the user, these processes are integral

stages of the software compilation process that extract the best possible circuit-level

implementation of the software application.

Scheduling

Scheduling is the process of identifying the data and control dependencies between

different operations to determine when each will execute. In traditional FPGA design, this is

a manual process also referred to as parallelizing the software algorithm for a hardware

implementation.

Vivado HLS analyzes dependencies between adjacent operations as well as across time. This

allows the compiler to group operations to execute in the same clock cycle and to set up the

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