Intel® AVX编程参考手册：并行指令集详解

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本资源是《Intel® Advanced Vector Extensions Programming Reference.pdf》文档，它是一份详细的Intel并行指令集编程手册，发布于2011年6月。这份文档主要涵盖了Intel的高级向量扩展（Advanced Vector Extensions，AVX）技术，这是英特尔处理器中用于加速浮点和整数运算的指令集，旨在提升计算性能和效率。 AVX是一种向后兼容的技术，它在保持向老版本处理器兼容的同时，提供了更强大的并行处理能力。该文档详细介绍了如何利用这些扩展来编写高性能的多线程程序，包括对新指令集特性的介绍、编译器支持、硬件要求以及潜在的优化策略。值得注意的是，尽管AVX提供了丰富的功能，但开发者必须意识到文档中提到的“保留”或“未定义”特性可能存在不确定性，不适当的使用可能会导致不可预测的行为或软件代码故障。对于开发人员来说，这份手册是理解和利用AVX的重要参考资料，它覆盖了指令集的架构、指令集指令的描述、内存操作、数据类型以及与CPU缓存、向量化加载/存储等核心概念的深入解析。同时，手册还强调了英特尔产品的使用限制，如不得用于医疗、生命维持或关键应用，因为这些应用的安全性和可靠性要求非常高。学习和遵循手册中的指导，可以帮助开发者最大限度地发挥Intel处理器的性能潜力，同时避免潜在的风险和错误。此外，由于Intel可能随时对规格和产品描述进行更新，开发者应持续关注最新的技术文档，以确保他们的代码能适应不断演进的硬件环境。《Intel® Advanced Vector Extensions Programming Reference.pdf》是一份必备的工具，对于想要利用AVX进行高性能计算的程序员来说，它不仅提供了技术细节，也包含了必要的注意事项和最佳实践，是优化现代计算机程序性能的重要参考资料。

1-2 Ref. # 319433-011

INTEL® ADVANCED VECTOR EXTENSIONS

functionality and vector lengths by introducing an efficient instruction encoding

scheme, three and four operand instruction syntax, supporting load and store

masking, etc.

Intel Advanced Vector Extensions offers comprehensive architectural enhance-

ments and functional enhancements in arithmetic as well as data processing prim-

itives. Section 1.3 summarizes the architectural enhancement of AVX. Functional

overview of AVX and FMA instructions are summarized in Section 1.5. General-pur-

pose encryption and AES instructions follow the existing architecture of 128-bit

SIMD instruction sets like SSE4 and its predecessors, Section 1.6 provides a short

summary.

1.3 INTEL® ADVANCED VECTOR EXTENSIONS

ARCHITECTURE OVERVIEW

Intel AVX has many similarities to the SSE and double-precision floating-point por-

tions of SSE2. However, Intel AVX introduces the following architectural enhance-

ments:

• Support for 256-bit wide vectors and SIMD register set. 256-bit register state is

managed by Operating System using XSAVE/XRSTOR instructions introduced in

45 nm Intel 64 processors (see IA-32 Intel® Architecture Software Developer’s

Manual, Volumes 2B and 3A).

• Instruction syntax support for generalized three-operand syntax to improve

instruction programming flexibility and efficient encoding of new instruction

extensions.

• Enhancement of legacy 128-bit SIMD instruction extensions to support three-

operand syntax and to simplify compiler vectorization of high-level language

expressions.

• Instruction encoding format using a new prefix (referred to as VEX) to provide

compact, efficient encoding for three-operand syntax, vector lengths,

compaction of SIMD prefixes and REX functionality.

• FMA extensions and enhanced floating-point compare instructions add support

for IEEE-754-2008 standard.

1.3.1 256-Bit Wide SIMD Register Support

Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7 in oper-

ating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode). The lower 128-

bits of the YMM registers are aliased to the respective 128-bit XMM registers.

1-4 Ref. # 319433-011

INTEL® ADVANCED VECTOR EXTENSIONS

Note SIMD instructions supporting three-operand syntax but processing only 128-

bits of data are considered part of the 256-bit SIMD instruction set extensions of

AVX, because bits 255:128 of the destination register are zeroed by the processor.

1.3.3 VEX Prefix Instruction Encoding Support

Intel AVX introduces a new prefix, referred to as VEX, in the Intel 64 and IA-32

instruction encoding format. Instruction encoding using the VEX prefix provides the

following capabilities:

• Direct encoding of a register operand within VEX. This provides instruction syntax

support for non-destructive source operand.

• Efficient encoding of instruction syntax operating on 128-bit and 256-bit register

sets.

• Compaction of REX prefix functionality: The equivalent functionality of the REX

prefix is encoded within VEX.

• Compaction of SIMD prefix functionality and escape byte encoding: The function-

ality of SIMD prefix (66H, F2H, F3H) on opcode is equivalent to an opcode

extension field to introduce new processing primitives. This functionality is

replaced by a more compact representation of opcode extension within the VEX

prefix. Similarly, the functionality of the escape opcode byte (0FH) and two-byte

escape (0F38H, 0F3AH) are also compacted within the VEX prefix encoding.

• Most VEX-encoded SIMD numeric and data processing instruction semantics with

memory operand have relaxed memory alignment requirements than instruc-

tions encoded using SIMD prefixes (see Section 2.5).

VEX prefix encoding applies to SIMD instructions operating on YMM registers, XMM

registers, and in some cases with a general-purpose register as one of the operand.

VEX prefix is not supported for instructions operating on MMX or x87 registers.

Details of VEX prefix and instruction encoding are discussed in Chapter 4.

1.4 OVERVIEW AVX2

AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions

with 256-bit numeric processing capabilities. AVX2 instructions follow the same

programming model as AVX instructions.

In addition, AVX2 provide enhanced functionalities for broadcast/permute operations

on data elements, vector shift instructions with variable-shift count per data

element, and instructions to fetch non-contiguous data elements from memory.

Ref. # 319433-011 1-5

INTEL® ADVANCED VECTOR EXTENSIONS

1.5 FUNCTIONAL OVERVIEW

Intel AVX and FMA provide comprehensive functional improvements over previous

generations of SIMD instruction extensions. The functional improvements include:

• 256-bit floating-point arithmetic primitives: AVX enhances existing 128-bit

floating-point arithmetic instructions with 256-bit capabilities for floating-point

processing. FMA provides additional set of 256-bit floating-point processing

capabilities with a rich set of fused-multiply-add and fused multiply-subtract

primitives.

• Enhancements for flexible SIMD data movements: AVX provides a number of

new data movement primitives to enable efficient SIMD programming in relation

to loading non-unit-strided data into SIMD registers, intra-register SIMD data

manipulation, conditional expression and branch handling, etc. Enhancements

for SIMD data movement primitives cover 256-bit and 128-bit vector floating-

point data, and 128-bit integer SIMD data processing using VEX-encoded instruc-

tions.

Several key categories of functional improvements in AVX and FMA are summarized

in the following subsections.

1.5.1 256-bit Floating-Point Arithmetic Processing Enhancements

Intel AVX provides 35 256-bit floating-point arithmetic instructions. The arithmetic

operations cover add, subtract, multiply, divide, square-root, compare, max, min,

round, etc., on single-precision and double-precision floating-point data.

The enhancement in AVX on floating-point compare operation provides 32 condi-

tional predicates to improve programming flexibility in evaluating conditional expres-

sions.

FMA provides 36 256-bit floating-point instructions to perform computation on 256-

bit vectors. The arithmetic operations cover fused multiply-add, fused multiply-

subtract, fused multiply add/subtract interleave, signed-reversed multiply on fused

multiply-add and multiply-subtract.

1.5.2 256-bit Non-Arithmetic Instruction Enhancements

Intel AVX provides new primitives for handling data movement within 256-bit

floating-point vectors and promotes many 128-bit floating data processing instruc-

tions to handle 256-bit floating-point vectors.

AVX includes 39 256-bit data processing instructions that are promoted from

previous generations of SIMD instruction extensions, ranging from logical, blend,

convert, test, unpacking, shuffling, load and stores.

AVX introduces 18 new data processing instructions that operate on 256-bit vectors.

These new primitives cover the following operations:

1-6 Ref. # 319433-011

INTEL® ADVANCED VECTOR EXTENSIONS

• Non-unit-stride fetching of SIMD data. AVX provides several flexible SIMD

floating-point data fetching primitives:

— broadcast of single or multiple data elements into a 256-bit destination,

— masked move primitives to load or store SIMD data elements conditionally,

• Intra-register manipulation of SIMD data elements. AVX provides several flexible

SIMD floating-point data manipulation primitives:

— insert/extract multiple SIMD floating-point data elements to/from 256-bit

SIMD registers

— permute primitives to facilitate efficient manipulation of floating-point data

elements in 256-bit SIMD registers

• Branch handling. AVX provides several primitives to enable handling of branches

in SIMD programming:

— new variable blend instructions supports four-operand syntax with non-

destructive source syntax. This is more flexible than the equivalent SSE4

instruction syntax which uses the XMM0 register as the implied mask for

blend selection.

— Packed TEST instructions for floating-point data.

1.5.3 Arithmetic Primitives for 128-bit Vector and Scalar

processing

Intel AVX provides 131 128-bit numeric processing instructions that employ VEX-

prefix encoding. These VEX-encoded instructions generally provide the same func-

tionality over instructions operating on XMM register that are encoded using SIMD

prefixes. The 128-bit numeric processing instructions in AVX cover floating-point and

integer data processing across 128-bit vector and scalar processing.

The enhancement in AVX on 128-bit floating-point compare operation provides 32

conditional predicates to improve programming flexibility in evaluating conditional

expressions. This contrasts with floating-point SIMD compare instructions in SSE and

SSE2 supporting only 8 conditional predicates.

FMA provides 60 128-bit floating-point instructions to process 128-bit vector and

scalar data. The arithmetic operations cover fused multiply-add, fused multiply-

subtract, signed-reversed multiply on fused multiply-add and multiply-subtract.

1.5.4 Non-Arithmetic Primitives for 128-bit Vector and Scalar

Processing

Intel AVX provides 126 data processing instructions that employ VEX-prefix

encoding. These VEX-encoded instructions generally provide the same functionality

over instructions operating on XMM register that are encoded using SIMD prefixes.

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