DDR2 SDRAM规格与特性：MT47H128M4
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"DDR2 SDRAM是内存技术的一种，由Micron公司生产的MT47H128M4型号是一款512Mb容量的DDR2 SDRAM芯片，它具有四倍数据预取（4n-bit prefetch）架构和四个内部银行，支持并发操作。该芯片设计符合JEDEC的1.8V I/O标准，工作电压为VDD=1.8V±0.1V，数据线VDDQ同样为1.8V±0.1V，并且提供了差分数据 strobe (DQS, DQS#)选项。此外，它还具备DLL功能，用于同步DQ和DQS信号与时钟CK的转换。MT47H128M4支持可编程的CAS延迟(CL)，以及附加写入延迟(AL)，写入延迟等于读取延迟减去1个时钟周期(tCK)。芯片的突发长度可选4或8，允许调整数据输出驱动强度，并且具有64ms、8192周期的刷新率。"
DDR2 SDRAM的主要特性包括：
1. **电压标准**：DDR2 SDRAM的工作电压较低，VDD和VDDQ均为1.8V，这有助于降低系统功耗。
2. **数据预取**：4n-bit预取架构使得数据传输效率更高，数据传输速率更快。
3. **内部银行**：四内部银行的设计使得数据访问更加并发，提高了内存性能。
4. **DQS信号**：差分数据 strobe 提供了更精确的数据同步，增强了信号完整性。
5. **DLL**：延迟锁相环(DLL)确保数据和时钟之间的精确对齐。
6. **CAS延迟**：可编程的CAS延迟(CL)允许根据系统需求调整读取延迟。
7. **附加写入延迟**：写入延迟等于读取延迟减去1个时钟周期，优化了写操作的时序。
8. **突发长度**：支持4和8的突发长度，提供了灵活的内存访问模式。
9. **输出驱动强度**：可调整的数据输出驱动强度可以根据系统需求进行优化。
10. **刷新机制**：64ms的刷新周期和8192次刷新循环保证了数据在内存中的稳定性。
11. **温度选项**：提供工业级(IT)和汽车级(AT)温度选项，适应不同应用环境。
12. **环保认证**：符合RoHS标准，无铅封装。
13. **包封选项**：包括不同引脚数的FBGA封装，如84-ball和60-ball FBGA，以适应不同尺寸和引脚布局的需求。
DDR2 SDRAM是一种高性能、低电压的内存解决方案，广泛应用于计算机和其他电子设备中，提供高效的内存访问和数据处理能力。Micron的MT47H128M4则是这一领域的典型产品，其特性设计充分考虑了速度、能效和兼容性。
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions
Symbol Type Description
A[12:0] (x16)
A[13:0] (x4, x8)
Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[1:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
BA0, BA1 Input Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[1:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-
er-down (row active in any bank). CKE is synchronous for power-down entry, power-
down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-
FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once V
DD
is applied during first pow-
er-up. After V
REF
has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, V
REF
must be maintained.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered high. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
LDM, UDM, DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for
upper byte DQ[15:8].
ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
DQ[15:0] (x16)
DQ[3:0] (x4)
DQ[7:0] (x8)
I/O Data input/output: Bidirectional data bus for 32 Meg x 16.
Bidirectional data bus for 128 Meg x 4.
Bidirectional data bus for 64 Meg x 8.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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