Philips Semiconductors
PCF8563
Real-time clock/calendar
Product specification 16 April 1999 6 of 30
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
[1] Not coded in BCD.
8.6.1 Control/Status 1 register
Table 5: BCD formatted registers overview
Bit positions labelled as ‘
−
’are not implemented.
Address Register name BCD format tens nibble BCD format units nibble
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
3
2
2
2
1
2
0
2
3
2
2
2
1
2
0
02H Seconds VL <seconds 00 to 59 coded in BCD>
03H Minutes − <minutes 00 to 59 coded in BCD>
04H Hours −− <hours 00 to 23 coded in BCD>
05H Days −− <days 01 to 31 coded in BCD>
06H Weekdays −−−−− <weekdays 0 to 6 >
[1]
07H Months/Century C −− <months 01 to 12 coded in BCD>
08H Years <years 00 to 99 coded in BCD>
09H Minute alarm AE <minute alarm 00 to 59 coded in BCD>
0AH Hour alarm AE − <hour alarm 00 to 23 coded in BCD>
0BH Day alarm AE − <day alarm 01 to 31 coded in BCD>
0CH Weekday alarm AE −−−− <weekday alarm 0 to 6 >
[1]
Table 6: Control/Status 1 register bits description (address 00H)
Bit Symbol Description
7 TEST1 TEST1 = 0; normal mode.
TEST1 = 1; EXT_CLK test mode; see Section 8.7.
5 STOP STOP = 0; RTC source clock runs.
STOP = 1; all RTC divider chain flip-flops are asynchronously set
to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still
available).
3 TESTC TESTC = 0; power-on reset override facility is disabled (set to logic 0
for normal operation).
TESTC = 1; power-on reset override is enabled.
6, 4, 2 to 0 0 By default set to logic 0.