Micron DDR4 MT40A系列规格详解

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Micron DDR4 SDRAM的规格书主要涵盖了MT40A1G4、MT40A512M8以及MT40A256M16这几种型号的DDR4内存芯片，详细描述了它们的技术特性和功能。 DDR4 SDRAM是第四代动态随机存取存储器，相比之前的DDR3，它在速度、功耗和容量方面都有显著提升。MT40A系列芯片的工作电压降低到1.2V±60mV（VDD=VDDQ），这不仅降低了运行时的功率消耗，也提高了能效。同时，VPP电源为2.5V，具有一定的电压调整范围，以适应不同的系统需求。这些内存芯片采用内部可调的VREFDQ生成，确保数据线参考电压的精确性，从而提高信号完整性。1.2V的伪开漏I/O（Open-Drain）设计有助于降低信号间的干扰，提高系统的稳定性。在温度范围内（0°C至95°C），DDR4内存芯片需执行64ms的8192周期刷新操作（在0°C至85°C），在高温环境下（85°C至95°C）则需缩短至32ms，以保持数据的稳定性。芯片内部有16个x4或8个x16的银行结构，分组管理，以及8n-bit的预取架构，这优化了数据访问效率。 DDR4内存支持编程数据 strobe预兆（Programmable data strobe preamble）、数据 strobe训练，以及命令/地址延迟（CAL），这允许系统根据硬件平台进行微调，以达到最佳性能。此外，还有多用途寄存器的读写能力，写入和读取校准，自刷新模式，低功耗自刷新（LPASR），温度控制的刷新（TCR），精细颗粒度刷新，自刷新终止等功能，确保了内存的节能和可靠性。为了增强系统的错误检测和纠正能力，DDR4内存芯片提供了数据总线反转（DBI）、命令/地址（CA）奇偶校验、数据总线写循环冗余检查（CRC）等特性。每个DRAM芯片都具有独立的地址寻址能力，增强了系统的故障容错能力。连接性测试（x16）和后封装修复（PPR）及软后封装修复（sPPR）模式则进一步确保了生产过程中的良品率和可维修性。 Micron的DDR4 SDRAM产品具备高效、节能和可靠的特点，广泛应用于高性能计算、数据中心、服务器和其他对内存性能有高要求的应用场景。这些技术特性确保了内存的稳定运行和系统的整体性能。

Table 103: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 277

Table 104: CK Overshoot and Undershoot/ Specifications .............................................................................. 278

Table 105: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 279

Table 106: Single-Ended Output Levels ......................................................................................................... 279

Table 107: Single-Ended Output Slew Rate Definition .................................................................................... 280

Table 108: Single-Ended Output Slew Rate .................................................................................................... 281

Table 109: Differential Output Levels ............................................................................................................. 281

Table 110: Differential Output Slew Rate Definition ....................................................................................... 281

Table 111: Differential Output Slew Rate ....................................................................................................... 282

Table 112: Connectivity Test Mode Output Levels .......................................................................................... 283

Table 113: Connectivity Test Mode Output Slew Rate ..................................................................................... 284

Table 114: Strong Mode (34Ω) Output Driver Electrical Characteristics ........................................................... 286

Table 115: Weak Mode (48Ω) Output Driver Electrical Characteristics ............................................................. 287

Table 116: Output Driver Sensitivity Definitions ............................................................................................ 288

Table 117: Output Driver Voltage and Temperature Sensitivity ....................................................................... 288

Table 118: Alert Driver Voltage ...................................................................................................................... 289

Table 119: ODT DC Characteristics ............................................................................................................... 290

Table 120: ODT Sensitivity Definitions .......................................................................................................... 291

Table 121: ODT Voltage and Temperature Sensitivity ..................................................................................... 291

Table 122: ODT Timing Definitions ............................................................................................................... 292

Table 123: Reference Settings for ODT Timing Measurements ........................................................................ 292

Table 124: DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 295

Table 125: DRAM Package Electrical Specifications for x16 Devices ................................................................ 296

Table 126: Pad Input/Output Capacitance ..................................................................................................... 298

Table 127: Thermal Characteristics ............................................................................................................... 299

Table 128: Basic I

, I

, and I

DDQ

Measurement Conditions .......................................................................... 301

Table 129: I

DD0

and I

PP0

Measurement-Loop Pattern

.................................................................................... 305

Table 130: I

DD1

Measurement-Loop Pattern

................................................................................................. 306

Table 131: I

DD2N

, I

DD3N

, and I

PP3P

Measurement-Loop Pattern

...................................................................... 307

Table 132: I

DD2NT

and I

DDQ2NT

Measurement-Loop Pattern

........................................................................... 308

Table 133: I

DD4R

and I

DDQ4R

Measurement-Loop Pattern

.............................................................................. 309

Table 134: I

DD4W

Measurement-Loop Pattern

............................................................................................... 310

Table 135: I

DD4Wc

Measurement-Loop Pattern

.............................................................................................. 311

Table 136: I

DD5b

Measurement-Loop Pattern

................................................................................................ 312

Table 137: I

DD7

Measurement-Loop Pattern

................................................................................................. 313

Table 138: Timings used for I

, I

, and I

DDQ

Measurement-Loop Patterns .................................................... 314

Table 139: I

, I

, and I

DDQ

Current Limits – Rev. A ....................................................................................... 315

Table 140: I

, I

, and I

DDQ

Current Limits – Rev. B ....................................................................................... 316

Table 141: DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 319

Table 142: DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 320

Table 143: DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 321

Table 144: DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 322

Table 145: DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 323

Table 146: DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 324

Table 147: DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 326

Table 148: Refresh Parameters by Device Density ........................................................................................... 328

Table 149: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 ................... 329

Table 150: Electrical Characteristics and AC Timing Parameters ..................................................................... 341

Table 151: Die Revision Options .................................................................................................................... 353

Table 152: Speed Options ............................................................................................................................. 354

Table 153: Width Options ............................................................................................................................. 354

4Gb: x4, x8, x16 DDR4 SDRAM

Features

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. E 11/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

General Notes and Description

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-

ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach-

ieve high-speed operation. The 8n-prefetch architecture is combined with an interface

designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit

wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit

wide, one-half-clock-cycle data transfers at the I/O pins. on page

Industrial Temperature

An industrial temperature (IT) device option requires that the case temperature not ex-

ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double

when T

exceeds 85°C; this also requires use of the high-temperature self refresh option.

Additionally, ODT resistance and the input/output impedance must be derated when

operating outside of the commercial temperature range, when T

is between -40°C and

0°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation), unless specifically stated other-

wise.

• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise.

• The terms "_t" and "_c" are used to represent the true and complement of a differen-

tial signal pair. These terms replace the previously used notation of "#" and/or over-

bar characters. For example, differential data strobe pair DQS, DQS# is now referred

to as DQS_t, DQS_c.

• The term "_n" is used to represent a signal that is active LOW and replaces the previ-

ously used "#" and/or overbar characters. For example: CS# is now referred to as

CS_n.

• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as

DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the entire document; any page

or diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated here within is considered undefined, illegal,

and not supported, and can result in unknown operation.

• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for

row/col address.

• The NOP command is not allowed, except when exiting maximum power savings

mode or when entering gear-down mode, and only a DES command should be used.

4Gb: x4, x8, x16 DDR4 SDRAM

General Notes and Description

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. E 11/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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