Intel 82599 10GbE 控制器V3.4规格说明书：全面特性和功能概述

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Intel 82599 10GbE Controller Datasheet (Revision 3.4)发布于2019年11月，是针对双端口10 GbE设备或单端口版本（82599 EN）的专业级PCIE网卡。该文档详述了这款网卡的关键特性和技术规格。首先，82599集成了多种接口，包括串行闪存接口和4线SPI EEPROM接口，使得它具备灵活的配置能力，支持软件或OEM定制，例如可编程的LED操作，用于显示不同的状态信息。此外，它还提供了一个受保护的EEPROM空间，用于存储私有配置数据，确保数据的安全性。在功能上，82599符合多个高速以太网标准，包括10 Gb/s Ethernet、802.3ap（KX/KX4/KR）、10 Gb/s Ethernet/802.3ae（XAUI）以及1000BASE-BX标准，这意味着它可以处理高速的数据传输。它支持高达15.5 KB的大包（jumbo frames），有助于优化网络性能。此外，它遵循自动协商 Clause 73，确保与不同设备间的兼容性。在流量控制方面，82599支持发送和接收PAUSE帧，以及接收FIFO阈值设置，这有助于在网络拥塞时保持稳定通信。统计信息用于网络管理和RMON（远程监控）功能，便于管理员对网络状况进行实时监控和维护。 82599还支持802.1q VLAN，允许对网络流量进行分段和管理，提高了网络安全性。其强大的TCP/IP处理能力包括256 KB的TCP段分片卸载，减少了CPU负载。对于IPv6的支持，它实现了IP/TCP和IP/UDP的接收校验和卸载，同时提供分片UDP校验和卸载功能，以加速处理和重组破碎的UDP数据包。最后，82599集成了高级协议处理能力，如TCP段接收检查、IPv6支持，以及UDP碎片校验和卸载，这些特性都体现了其在现代数据中心和企业网络中的高性能和可靠性。 Intel 82599 10GbE Controller Datasheet（Rev 3.4）提供了全面的硬件特性，适合需要高效、可靠和可扩展网络连接的应用场景，无论是云计算、数据中心还是企业级网络环境都能发挥出色性能。

Intel

82599 10 GbE Controller—Contents

16 331520-005

7.11.6 RSC Completion and Aging .......................................................................................... 472

7.12 IPsec Support .......................................................................................................................... 474

7.12.1 Overview ..................................................................................................................474

7.12.2 Hardware Features List ............................................................................................... 474

7.12.3 Software/Hardware Demarcation.................................................................................. 477

7.12.4 IPsec Formats Exchanged Between Hardware and Software ............................................. 478

7.12.5 Tx SA Table...............................................................................................................482

7.12.6 Tx Hardware Flow ...................................................................................................... 483

7.12.7 AES-128 Operation in Tx ............................................................................................. 485

7.12.8 Rx Descriptors ...........................................................................................................487

7.12.9 Rx SA Tables ............................................................................................................. 487

7.12.10 Rx Hardware Flow without TCP/UDP Checksum Offload.................................................... 490

7.12.11 Rx Hardware Flow with TCP/UDP Checksum Offload ........................................................ 491

7.12.12 AES-128 Operation in Rx............................................................................................. 491

7.13 Fibre Channel over Ethernet (FCoE) ............................................................................................ 493

7.13.1 Introduction ..............................................................................................................493

7.13.2 FCoE Transmit Operation............................................................................................. 494

7.13.3 FCoE Receive Operation .............................................................................................. 500

7.14 Reliability ................................................................................................................................ 516

7.14.1 Memory Integrity Protection ........................................................................................ 516

7.14.2 PCIe Error Handling.................................................................................................... 516

8.0 Programming Interface .........................................................................................517

8.1 Address Regions ....................................................................................................................... 517

8.1.1 Memory-Mapped Access .............................................................................................. 517

8.1.2 I/O-Mapped Access..................................................................................................... 518

8.1.3 Registers Terminology ................................................................................................ 520

8.2 Device Registers — PF ............................................................................................................... 521

8.2.1 MSI-X BAR Register Summary PF ................................................................................. 521

8.2.2 Registers Summary PF — BAR 0................................................................................... 521

8.2.3 Detailed Register Descriptions — PF.............................................................................. 541

8.3 Device Registers — VF .............................................................................................................. 732

8.3.1 Registers Allocated Per Queue...................................................................................... 732

8.3.2 Non-Queue Registers.................................................................................................. 732

8.3.3 MSI—X Register Summary VF — BAR 3 ......................................................................... 733

8.3.4 Registers Summary VF — BAR 0................................................................................... 735

8.3.5 Detailed Register Descriptions —VF............................................................................... 737

9.0 PCIe Programming Interface ................................................................................747

9.1 PCI Compatibility ...................................................................................................................... 747

9.2 Configuration Sharing Among PCI Functions ................................................................................. 748

9.3 PCIe Register Map .................................................................................................................... 750

9.3.1 Register Attributes ..................................................................................................... 750

9.3.2 PCIe Configuration Space Summary.............................................................................. 750

9.3.3 Mandatory PCI Configuration Registers — Except BARs.................................................... 752

9.3.4 Subsystem ID Register (0x2E; RO) ............................................................................... 755

9.3.5 Cap_Ptr Register (0x34; RO) ....................................................................................... 755

9.3.6 Mandatory PCI Configuration Registers — BARs.............................................................. 756

9.3.7 PCIe Capabilities ........................................................................................................ 757

9.3.8 MSI-X Capability ........................................................................................................ 763

9.3.9 VPD Registers............................................................................................................ 768

9.3.10 PCIe Configuration Registers........................................................................................ 769

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Contents—Intel

82599 10 GbE Controller

9.4 PCIe Extended Configuration Space ............................................................................................. 780

9.4.1 Advanced Error Reporting Capability (AER) .................................................................... 781

9.4.2 Serial Number............................................................................................................ 786

9.4.3 Alternate Routing ID Interpretation (ARI) Capability Structure.......................................... 788

9.4.4 IOV Capability Structure.............................................................................................. 789

9.5 Virtual Functions Configuration Space .......................................................................................... 796

9.5.1 Mandatory Configuration Space ....................................................................................798

9.5.2 PCI Capabilities..........................................................................................................800

10.0 Manageability .......................................................................................................803

10.1 Platform Configurations ............................................................................................................. 803

10.1.1 On-Board BMC Configurations ...................................................................................... 803

10.1.2 82599 NIC.................................................................................................................804

10.2 Pass-Through (PT) Functionality ................................................................................................. 804

10.2.1 DMTF NC-SI Mode ......................................................................................................805

10.2.2 SMBus Pass-Through (PT) Functionality.........................................................................807

10.3 Manageability Receive Filtering ................................................................................................... 811

10.3.1 Overview and General Structure...................................................................................811

10.3.2 L2 EtherType Filters.................................................................................................... 813

10.3.3 VLAN Filters - Single and Double VLAN Cases ................................................................. 813

10.3.4 L3 and L4 Filters ........................................................................................................814

10.3.5 Manageability Decision Filters ...................................................................................... 816

10.3.6 Possible Configurations ...............................................................................................818

10.4 LinkSec and Manageability ......................................................................................................... 820

10.4.1 Handover of LinkSec Responsibility Between BMC and Host.............................................. 821

10.5 Manageability Programming Interfaces ........................................................................................ 824

10.5.1 NC-SI Programming....................................................................................................824

10.5.2 SMBus Programming................................................................................................... 873

10.5.3 Manageability Host Interface........................................................................................ 910

10.5.4 Software and Firmware Synchronization ........................................................................ 914

11.0 Electrical/Mechanical Specification .......................................................................917

11.1 Introduction .............................................................................................................................917

11.2 Operating Conditions ................................................................................................................ 917

11.2.1 Absolute Maximum Ratings .......................................................................................... 917

11.2.2 Recommended Operating Conditions ............................................................................. 918

11.3 Power Delivery ......................................................................................................................... 918

11.3.1 Power Supply Specifications......................................................................................... 918

11.3.2 In-Rush Current ......................................................................................................... 920

11.4 DC/AC Specification .................................................................................................................. 920

11.4.1 DC Specifications .......................................................................................................920

11.4.2 Digital I/F AC Specifications ......................................................................................... 925

11.4.3 PCIe Interface AC/DC Specification ...............................................................................936

11.4.4 Network (MAUI) Interface AC/DC Specification ............................................................... 937

11.4.5 SerDes Crystal/Reference Clock Specification ................................................................. 938

11.5 Package .................................................................................................................................. 943

11.5.1 Mechanical ................................................................................................................943

11.5.2 Thermal ....................................................................................................................943

11.5.3 Electrical ................................................................................................................... 943

11.5.4 Mechanical Package .................................................................................................... 944

11.6 Devices Supported .................................................................................................................... 944

11.6.1 Flash ........................................................................................................................ 944

Intel

82599 10 GbE Controller—Contents

18 331520-005

11.6.2 EEPROM....................................................................................................................945

12.0 Design Considerations and Guidelines ...................................................................947

12.1 Connecting the PCIe Interface .................................................................................................... 947

12.1.1 Link Width Configuration ............................................................................................. 947

12.1.2 Polarity Inversion and Lane Reversal............................................................................. 948

12.1.3 PCIe Reference Clock.................................................................................................. 948

12.1.4 PCIe Analog Bias Resistor............................................................................................ 948

12.1.5 Miscellaneous PCIe Signals .......................................................................................... 948

12.1.6 PCIe Layout Recommendations .................................................................................... 948

12.2 Connecting the MAUI Interfaces ................................................................................................. 949

12.2.1 MAUI Channels Lane Connections ................................................................................. 949

12.2.2 MAUI Bias Resistor ..................................................................................................... 949

12.2.3 XAUI, KX/KR, BX4, CX4, BX and SFI+ Layout Recommendations ...................................... 949

12.2.4 Board Stack-Up Example............................................................................................. 950

12.2.5 Trace Geometries....................................................................................................... 950

12.2.6 Other High-Speed Signal Routing Practices .................................................................... 951

12.2.7 Reference Planes........................................................................................................ 954

12.2.8 Dielectric Weave Compensation.................................................................................... 956

12.2.9 Impedance Discontinuities........................................................................................... 957

12.2.10 Reducing Circuit Inductance......................................................................................... 957

12.2.11 Signal Isolation.......................................................................................................... 958

12.2.12 Power and Ground Planes............................................................................................ 958

12.2.13 KR and SFI+ Recommended Simulations ....................................................................... 964

12.2.14 Additional Differential Trace Layout Guidelines for SFI+ Boards ........................................ 965

12.3 Connecting the Serial EEPROM ................................................................................................... 967

12.3.1 Supported EEPROM Devices......................................................................................... 967

12.4 Connecting the Flash ................................................................................................................ 967

12.4.1 Supported Flash Devices ............................................................................................. 968

12.5 SMBus and NC-SI ..................................................................................................................... 968

12.6 NC-SI ..................................................................................................................................... 970

12.6.1 NC-SI Design Requirements......................................................................................... 970

12.6.2 NC-SI Layout Requirements......................................................................................... 972

12.7 Resets .................................................................................................................................... 977

12.8 Connecting the MDIO Interfaces ................................................................................................. 978

12.9 Connecting the Software-Definable Pins (SDPs) ............................................................................ 978

12.10 Connecting the Light Emitting Diodes (LEDs) ................................................................................ 978

12.11 Connecting Miscellaneous Signals ............................................................................................... 979

12.11.1 LAN Disable............................................................................................................... 979

12.11.2 BIOS Handling of Device Disable .................................................................................. 980

12.12 Oscillator Design Considerations ................................................................................................. 980

12.12.1 Oscillator Types .........................................................................................................981

12.12.2 Oscillator Solution ......................................................................................................981

12.12.3 Oscillator Layout Recommendations.............................................................................. 982

12.12.4 Reference Clock Measurement Recommendations ........................................................... 982

12.13 Power Supplies ........................................................................................................................ 982

12.13.1 Power Supply Sequencing............................................................................................ 982

12.13.2 Power Supply Filtering ................................................................................................ 983

12.13.3 Support for Power Management and Wake Up ................................................................ 983

12.14 Connecting the JTAG Port .......................................................................................................... 984

13.0 Thermal Design Recommendations .......................................................................985

331520-005 19

Contents—Intel

82599 10 GbE Controller

13.1 Thermal Considerations .............................................................................................................985

13.2 Importance of Thermal Management ...........................................................................................986

13.3 Packaging Terminology .............................................................................................................. 986

13.4 Thermal Specifications .............................................................................................................. 987

13.5 Case Temperature .................................................................................................................... 988

13.6 Thermal Attributes .................................................................................................................... 988

13.6.1 Designing for Thermal Performance .............................................................................. 988

13.6.2 Model System Definition..............................................................................................988

13.6.3 Package Thermal Characteristics .................................................................................. 989

13.7 Thermal Enhancements ............................................................................................................. 990

13.8 Clearances ............................................................................................................................... 990

13.9 Default Enhanced Thermal Solution ............................................................................................. 992

13.10 Extruded Heatsinks ................................................................................................................... 993

13.11 Attaching the Extruded Heatsink .................................................................................................994

13.11.1 Clips......................................................................................................................... 994

13.11.2 Thermal Interface (PCM45 Series) ................................................................................ 994

13.11.3 Avoid Damaging Die-Side Capacitors with Heat Sink Attached ..........................................994

13.11.4 Maximum Static Normal Load....................................................................................... 995

13.12 Reliability ................................................................................................................................ 996

13.12.1 Thermal Interface Management for Heatsink Solutions .................................................... 996

13.13 Measurements for Thermal Specifications .................................................................................... 997

13.13.1 Case Temperature Measurements................................................................................. 997

13.13.2 Attaching the Thermocouple (No Heatsink) .................................................................... 998

13.13.3 Attaching the Thermocouple (Heatsink) ......................................................................... 998

13.14 Heatsink and Attach Suppliers .................................................................................................... 999

13.15 PCB Guidelines ....................................................................................................................... 1000

14.0 Diagnostics ......................................................................................................... 1001

14.1 Link Loopback Operations ........................................................................................................ 1001

15.0 Glossary and Acronyms ....................................................................................... 1003

15.1 Register Attributes .................................................................................................................. 1014

Appendix A Packets and Frames................................................................................ 1015

A.1 Legacy Packet Formats ............................................................................................................ 1015

A.1.1 ARP Packet Formats ................................................................................................. 1015

A.1.2 IP and TCP/UDP Headers for TSO ............................................................................... 1017

A.1.3 Magic Packet ........................................................................................................... 1023

A.1.4 SNAP Packet Format................................................................................................. 1023

A.2 Packet Types for Packet Split Filtering ........................................................................................ 1023

A.2.1 Type 1.1: Ethernet (VLAN/SNAP) IP Packets ................................................................ 1024

A.2.2 Type 2: Ethernet, IPv6 ............................................................................................. 1033

A.2.3 Type 3: Reserved..................................................................................................... 1036

A.2.4 Type 4: NFS Packets ................................................................................................ 1036

A.3 IPsec Formats Run Over the Wire ..............................................................................................1041

A.3.1 AH Formats............................................................................................................. 1041

A.3.2 ESP Formats............................................................................................................ 1045

A.4 BCN Frame Format.................................................................................................................. 1050

A.5 FCoE Framing ......................................................................................................................... 1051

A.5.1 FCoE Frame Format.................................................................................................. 1051

A.5.2 FC Frame Format ..................................................................................................... 1054

Appendix B LESM - Link Establishment State Machine for the 82599 ......................... 1061

B.1 Background............................................................................................................................ 1061

B.2 Location in the NVM................................................................................................................. 1062

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