PIC24FJ128GA010：高性能16位单片机数据手册详解

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本文档是Microchip Technology Inc.在2005年至2012年期间发布的关于PIC24FJ128GA010系列单片机的数据手册，它提供了这款高性能处理器的详尽介绍。该单片机采用改良的哈佛架构，能够在32MHz时钟下实现高达16 MIPS的运算能力，展现出极高的性能。核心特性之一是其硬件配置：具有一个17位乘以17位的单周期硬件乘法器，以及一个32位除以16位的硬件分频器，这极大地提升了数据处理的效率。此外，它配备了16x16位的工作寄存器数组，这使得程序执行更加高效且灵活。指令集架构方面，采用了C编译器优化的设计，包含76种基础指令，支持多种灵活的地址模式，便于程序员进行高效编程。特别之处在于，有两个地址生成单元，能够独立处理数据内存的读写操作，增强了数据访问的灵活性。电源管理是这款单片机的另一个亮点，它支持从2.0V到3.6V的宽电压范围，确保了在不同应用环境下的稳定工作。存储器部分，Flash程序内存具有1000次擦写/写入循环，能满足长期存储需求，至少能保持20年的数据保留。并且，单片机具有自我重新编程的能力，可以根据软件控制进行固件升级。在低功耗模式方面，提供了睡眠、空闲和可选的交替时钟模式，有助于节省能源。此外，还具备失效安全时钟监测功能，当系统时钟出现故障时，会自动切换到内部低功耗RC振荡器，确保系统的可靠性。内部还包括一个2.5V稳压器，确保电路的电压稳定，以及集成的JTAG边界扫描和编程接口，方便开发和调试。电源相关的辅助功能还包括电源-on复位（POR）、电源上电定时器（PWRT）和振荡器启动定时器（OST）。同时，单片机还配备了一个灵活的看门狗定时器（WDT），在需要时可以提供额外的安全保障。 PIC24FJ128GA010是一款集高性能、低功耗、宽电压范围和多种高级功能于一体的单片机，适合对性能、稳定性及开发便利性有高要求的嵌入式系统设计。

PIC24FJ128GA010 FAMILY

DS39747F-page 16  2005-2012 Microchip Technology Inc.

RG0 — 75 90 I/O ST PORTG Digital I/O.

RG1 — 74 89 I/O ST

RG2374757I/OST

RG3364656I/OST

RG6 4 6 10 I/O ST

RG7 5 7 11 I/O ST

RG8 6 8 12 I/O ST

RG9 8 10 14 I/O ST

RG12 — — 96 I/O ST

RG13 — — 97 I/O ST

RG14 — — 95 I/O ST

RG15 — — 1 I/O ST

RTCC 42 54 68 O — Real-Time Clock Alarm Output.

SCK1 35 45 55 O — SPI1 Serial Clock Output.

SCK2 4 6 10 I/O ST SPI2 Serial Clock Output.

SCL1 37 47 57 I/O I

C I2C1 Synchronous Serial Clock Input/Output.

SCL2 32 52 58 I/O I

C I2C2 Synchronous Serial Clock Input/Output.

SDA1 36 46 56 I/O I

C I2C1 Data Input/Output.

SDA2 31 53 59 I/O I

C I2C2 Data Input/Output.

SDI1 34 44 54 I ST SPI1 Serial Data Input.

SDI2 5 7 11 I ST SPI2 Serial Data Input.

SDO1 33 43 53 O — SPI1 Serial Data Output.

SDO2 6 8 12 O — SPI2 Serial Data Output.

SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input.

SOSCO 48 60 74 O ANA Secondary Oscillator/Timer1 Clock Output.

SS1

14 18 23 I/O ST Slave Select Input/Frame Select Output (SPI1).

SS2

8 10 14 I/O ST Slave Select Input/Frame Select Output (SPI2).

T1CK 48 60 74 I ST Timer1 Clock.

T2CK — 4 6 I ST Timer2 External Clock Input.

T3CK — — 7 I ST Timer3 External Clock Input.

T4CK — 5 8 I ST Timer4 External Clock Input.

T5CK — — 9 I ST Timer5 External Clock Input.

TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input.

TDI 28 34 60 I ST JTAG Test Data/Programming Data Input.

TDO 24 14 61 O — JTAG Test Data Output.

TMS 23 13 17 I ST JTAG Test Mode Select Input.

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function

Pin Number

I/O

Input

Buffer

Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I

C™ = I

C/SMBus input buffer

 2005-2012 Microchip Technology Inc. DS39747F-page 19

PIC24FJ128GA010 FAMILY

2.0 GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FJ128GA010 family

family of 16-bit microcontrollers requires attention to a

minimal set of device pin connections before

proceeding with development.

The following pins must always be connected:

•All V

DD and VSS pins

(see Section 2.2 “Power Supply Pins”)

•All AV

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

•MCLR

(see Section 2.3 “Master Clear (MCLR) Pin”)

• ENVREG/DISVREG and V

CAP/VDDCORE pins

(PIC24F J devices only)

(see Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and V

CAP/VDDCORE)”)

These pins must also be connected if they are being

used in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

PIC24FJXXXX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

MCLR

VCAP/VDDCORE

(EN/DIS)VREG

(1)

(2)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and V

CAP/VDDCORE)”

for explanation of ENVREG/DISVREG pin

connections.

2: The example shown is for a PIC24F device

with five V

DD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

(1)

PIC24FJ128GA010 FAMILY

DS39747F-page 20  2005-2012 Microchip Technology Inc.

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as V

DD, VSS, AVDD and

SS is required.

Consider the following criteria when using decoupling

capacitors:

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

inductance.

2.2.2 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

not required in the end application, a direct

connection to V

DD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

voltage sags, may be beneficial. A typical

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR

pin. Consequently, specific voltage

levels (V

IH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR

pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

Any components associated with the MCLR

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR

pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR

from the external capacitor, C, in the

event of MCLR

pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR

IH and VIL specifications are met.

MCLR

PIC24FXXXX

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