Actel A3P系列FPGA数据手册：高容量，可重构，低功耗技术

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"ACTEL公司的A3P系列FPGA的数据手册提供了关于该系列器件的详细信息，包括供电、功耗、硬件资源、封装和引脚定义等。A3P系列FPGA支持可选的软核ARM处理器，适用于需要高性能、低功耗和高容量解决方案的系统设计。" ACTEL公司的A3P系列FPGA是一款基于130纳米7层金属（含6层铜）闪存技术的CMOS工艺产品，提供15千到1百万系统门的高容量设计空间。器件内嵌有高达144千比特的真正双端口SRAM，以及多达300个用户I/O，满足了复杂逻辑和存储需求。在性能方面，A3P系列FPGA能够实现350MHz的系统性能，支持3.3V、66MHz的64位PCI接口，确保了高速数据处理能力。其采用的分段化、层次化的路由和时钟结构，优化了信号传输效率，进一步提升了整体性能。为了适应不同的应用环境，A3P系列支持低功耗运行，可以提供1.5V核心电压选项，以满足仅1.5V系统的需要。此外，低阻抗闪存开关设计有助于降低功耗。器件还具备宽范围电源电压支持，根据JESD8-B标准，I/O可以在2.7V到3.6V之间操作，增加了设计灵活性。在安全性方面，A3P系列FPGA支持通过JTAG（符合IEEE 1532标准）进行在系统编程（ISP），并内置128位高级加密标准（AES）解密功能（ARM启用的ProASIC3设备除外），以保护设计内容。此外，FlashLock功能确保了FPGA内容的安全，防止未经授权的访问和修改。封装和引脚定义是设计人员进行硬件布局的关键信息，数据手册会详细介绍各种封装形式及各引脚的功能，便于设计人员根据实际需求选择合适的器件并进行正确的电路连接。 ACTEL公司的A3P系列FPGA结合了高容量、高性能、低功耗和强大的安全特性，适用于需要即时启动、可重新编程以及高性能嵌入式处理的广泛应用。对于那些需要在设计中集成软核ARM处理器的开发者来说，这是一个理想的平台。数据手册是深入理解和使用A3P系列FPGA的重要参考资料。

ProASIC3 DC and Switching Characteristics

2-2 Revision 13

Table 2-2 • Recommended Operating Conditions

1,2

Symbol Parameters

Commercial Industrial Units

Ambient temperature 0 to +70 -40 to +85 °C

Junction temperature 0 to 85 -40 to 100 °C

VCC

1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode

3.15 to 3.45 3.15 to 3.45 V

Operation

0 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V

VCCI and VMV

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.3 V wide range DC supply voltage

2.7 to 3.6 2.7 to 3.6 V

LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-18 on page 2-18.

4. The programming temperature range supported is T

ambient

= 0°C to 85°C.

5. VPUMP

can be left floating during operation (not programming mode).

6. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the

corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.

7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature

Product

Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature T

STG

(°C)

Maximum Operating

Junction Temperature T

(°C)

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3 Flash Family FPGAs

Revision 13 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC

3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for

information on clock and lock recovery.

Table 2-4 • Overshoot and Undershoot Limits

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/

Undershoot

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3 DC and Switching Characteristics

2-4 Revision 13

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

Thermal Characteristics

Introduction

The temperature variable in the Microsemi Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

= Junction Temperature = T + T

EQ 1

where:

= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = 

* P



= Junction-to-ambient of the package. 

numbers are located in Table 2-5.

P = Power dissipation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

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