MAX7000系列EEPROM可编程逻辑器件数据手册

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"EPM7128是一款基于第二代MAX架构的高性能、基于EEPROM的可编程逻辑器件（PLDs）。这款器件具有5.0V的在系统编程（ISP）功能，通过内置的IEEE Std.1149.1 JTAG接口在MAX7000S设备中实现。ISP电路与IEEE Std.1532兼容，适用于各种编程需求。EPM7128系列包括5.0V的MAX7000设备和5.0V的ISP型MAX7000S设备。对于带有128个或更多宏单元的MAX7000S设备，还集成了JTAG边界扫描测试（BST）电路。该系列涵盖了从600到5,000个可用门的完整EPLD家族，提供5ns的引脚到引脚逻辑延迟，最高可达175.4MHz的计数器频率（包括互连）。此外，还有符合PCI标准的设备。对于3.3V的MAX7000A和2.5V的MAX7000B设备，可以参考相应的数据手册了解更多信息。" EPM7128是Altera公司生产的CPLD（复杂可编程逻辑器件）之一，属于MAX7000系列。该系列器件的核心优势在于其高灵活性和在系统可编程性。5.0V的ISP功能使得用户能够在不拆卸设备的情况下进行编程和更新，大大提高了设计的便利性和适应性。这主要通过集成的IEEE Std.1149.1 JTAG接口实现，而且与IEEE Std.1532兼容，确保了与其他标准设备的兼容性。 EPM7128系列包含不同逻辑密度的器件，如EPM7032、EPM7064和EPM7096等，提供了广泛的门数选择，从600到5,000个可用门不等，满足不同规模和复杂性的电子设计需求。这些器件的逻辑延迟低至5ns，这意味着它们能够处理高速信号路径，支持高达175.4MHz的计数频率，这在当时的PLD技术中是非常出色的性能。 MAX7000S系列的一个重要特性是内置的JTAG边界扫描测试电路，这在拥有128个或更多宏单元的设备中特别有用。边界扫描测试是一种有效的故障诊断和调试工具，可以检查设备内部的各个部分，提高产品质量和可靠性。此外，EPM7128系列还考虑到了与现有标准的兼容性，如PCI标准，这使得它们可以直接应用于PCI总线接口的系统设计中，扩展了其应用范围。总体来说，EPM7128是适用于多种应用场景的高性能、灵活且易于编程的CPLD，尤其适合那些需要快速逻辑响应、在系统可编程性和高集成度的电子设计。无论是小规模的逻辑控制还是复杂的数字信号处理，EPM7128都能提供合适的解决方案。对于寻求不同电压操作的用户，还有3.3V的MAX7000A和2.5V的MAX7000B系列可供选择，这些信息可以在对应的数据手册中找到。

Altera Corporation 11

MAX 7000 Programmable Logic Device Family Data Sheet

Each programmable register can be clocked in three different modes:

■ By a global clock signal. This mode achieves the fastest clock-to-

output performance.

■ By a global clock signal and enabled by an active-high clock

enable. This mode provides an enable on each flipflop while still

achieving the fast clock-to-output performance of the global

clock.

■ By an array clock implemented with a product term. In this

mode, the flipflop can be clocked by signals from buried

macrocells or I/O pins.

In EPM7032, EPM7064, and EPM7096 devices, the global clock signal

is available from a dedicated clock pin, GCLK1, as shown in Figure 1.

In MAX 7000E and MAX 7000S devices, two global clock signals are

available. As shown in Figure 2, these global clock signals can be the

true or the complement of either of the global clock pins, GCLK1 or

GCLK2.

Each register also supports asynchronous preset and clear functions.

As shown in Figures 3 and 4, the product-term select matrix allocates

product terms to control these operations. Although the

product-term-driven preset and clear of the register are active high,

active-low control can be obtained by inverting the signal within the

logic array. In addition, each register clear function can be

individually driven by the active-low dedicated global clear pin

(GCLRn). Upon power-up, each register in the device will be set to a

low state.

All MAX 7000E and MAX 7000S I/O pins have a fast input path to a

macrocell register. This dedicated path allows a signal to bypass the

PIA and combinatorial logic and be driven to an input D flipflop with

an extremely fast (2.5 ns) input setup time.

Expander Product Terms

Although most logic functions can be implemented with the five

product terms available in each macrocell, the more complex logic

functions require additional product terms. Another macrocell can

be used to supply the required logic resources; however, the

MAX 7000 architecture also allows both shareable and parallel

expander product terms (“expanders”) that provide additional

product terms directly to any macrocell in the same LAB. These

expanders help ensure that logic is synthesized with the fewest

possible logic resources to obtain the fastest possible speed.

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