TI-UCD90320.pdf详细配置说明及应用示例集锦

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TI-UCD90320.pdf is a detailed document describing the features and functions of the UCD90320 power sequencer. This device is designed to manage the power distribution in a system, with capabilities such as voltage monitoring, current monitoring, and controlling various power supply outputs. The UCD90320 includes multiple input and output pins for communication with other components, such as the I2C/PMBus and JTAG interfaces. It also features a watchdog timer input from the main processor, as well as power good and system reset signals. The UCD90320 is capable of controlling and monitoring various power supply outputs, ranging from a 12V output to 0.8V and 1.8V outputs. It also includes features such as margining and synchronization capabilities, as well as hot swap and temperature monitoring functions. The device is designed to work in conjunction with other UCD90320 devices in a cascaded configuration to expand its capabilities. Overall, the UCD90320 is a versatile and comprehensive power sequencer that provides a high level of control and monitoring for complex power distribution systems. Its multiple features and interfaces make it a valuable component for managing power in a variety of applications.

UCD90320

ZHCSFI3B –AUGUST 2016–REVISED MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(7) PMBUS_CNTRL, PMBALERT, MARGIN19 and MARGIN20 pins have V

V33D

+ 0.3 V as maximum input voltage rating.

(8) I

specifications reflect the maximum current where the corresponding output voltage meets the V

thresholds.

(9) If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a

rare case), the internal reset time may be longer.

CONV

ADC conversion rate (on each ADC

channel)

(1)

1 MSPS

N ADC resolution 12 bits

Total unadjusted error, over full input

rangea when using internal reference

±10 ±30

LSB

Total unadjusted error, over full input range

when using external reference

±2.5 ±4

DIGITAL INPUTS AND OUTPUTS (GPIO, Logic GPO, EN, AND MARGIN PINS)

I/O high-level input voltage

(7)

0.65 ×

V33D

5.5 V

I/O low-level input voltage 0

0.35 ×

V33D

HYS

I/O input hysteresis 0.2 V

I/O high-level output voltage 2.4 V

I/O low-level output voltage 0.4 V

High-level source current V

= 2.4 V

(8)

4 mA

Low-level sink current V

= 0.4 V

(8)

4 mA

RESET AND BROWNOUT

V33DSlew

Minimum V33D slew rate between 2.8 V

and 3.2 V

0.1 V/ms

RESET

Supply voltage at which device comes out

of reset

2 2.3 2.6 V

BOR

Supply voltage at which device enters

brownout

2.93 3.02 3.11 V

SHDN

Supply voltage at which device shuts down 2.7 2.78 2.87 V

RESET

Minimum low-pulse width needed at

RESET



250 ns

IRT

Internal reset time

(9)

9 11.5 ms

7.6 Non-Volatile Memory Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CONFIGURATION FLASH MEMORY

CYC

Number of program and erase

cycles before failure

100,000 Cycles

RET

Data retention –40°C ≤ T

≤ 85°C 20 Years

FAULT AND EVENT LOGGING EEPROM

EPE

CYC

Number of mass program and erase

cycles of a single word before failure

500,000 Cycles

RET

Data retention –40°C ≤ T

≤ 85°C 20 Years

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