PN532模块详解：13.56MHz非接触通信寄存器指南

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"PN532文档-寄存器说明-带目录" 这篇文档详细介绍了PN532芯片，这是一款基于80C51微控制器核心的高度集成的13.56MHz非接触式通信收发模块。PN532支持六种不同的工作模式，使其在多种应用场景下具有广泛的应用： 1. ISO/IEC14443A/MIFARE阅读器/写入器：适用于与遵循此标准的卡片和标签进行通信。 2. FeliCa阅读器/写入器：支持FeliCa技术的设备交互。 3. ISO/IEC14443B阅读器/写入器：用于与遵循14443B标准的卡片交互。 4. MIFARE卡模拟：可以模拟MIFARE 1KB或MIFARE 4KB卡，实现卡片功能。 5. FeliCa卡模拟：能够模拟FeliCa卡片，提供相同功能。 6. ISO/IEC18092, ECMA-340点对点通信：支持近场通信（NFC）标准，允许设备之间直接交换数据。 PN532芯片具备处理ISO/IEC14443A帧格式和错误检测（奇偶校验和CRC）的能力，确保了与14443A标准卡片和标签的可靠通信。对于MIFARE产品，它支持更高的传输速度，双向可达424kbit/s。此外，PN532还能够解调和解码FeliCa编码信号，处理FeliCa帧格式和错误检测，同样支持424kbit/s的高速双向通信。这意味着PN532可以高效地与FeliCa系统中的设备进行数据交换。对于ISO/IEC14443B阅读器/写入器通信方案，PN532实现了第2层和第3层的功能，但文档中提到不包括特定的未详述的特性。这可能意味着PN532不负责某些特定的协议层交互，可能需要额外的软件或硬件支持来完成整个通信链路。在理解和应用PN532时，结合Libnfc库的文档以及命令手册是非常有帮助的，因为Libnfc是用于控制PN532等NFC芯片的开源库，它提供了与这些设备交互的API接口，使得开发者能够方便地实现非接触式通信功能，如读取和写入卡片数据、模拟卡片等。 PN532的寄存器说明部分会详细介绍芯片内部的配置和控制，这对于编程和调试PN532至关重要。寄存器设置直接影响到PN532的工作模式、通信参数以及错误处理机制。通过理解并正确操作这些寄存器，开发者可以精确地定制PN532的行为，以适应各种不同的非接触式通信需求。 PN532是一款功能强大的非接触式通信模块，支持多种标准和高速数据传输，而Libnfc库则提供了与之交互的工具，使得开发者能够轻松地在项目中集成PN532的功能，进行IC卡的读写、模拟以及其他NFC应用。

Product data sheet Rev. 3.2 — 3 December 2007 16 of 224

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

CONFIDENTIAL

8.1.4 PCON module

The Power Control (PCON) module is conﬁgured using the PCON SFR register.

8.1.5 Interrupt Controller

The interrupt controller has the following features:

• 13 interrupt sources

• Interrupt enable registers IE0 and IE1

• Interrupt priority registers IP0 and IP1

• Wake-up from Power-Down state

8.1.5.1 Interrupt vectors

The mapping between interrupt sources and interrupt vectors is shown in Table 9.

Table 7. PCON register (SFR: address 87h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SMOD - CPU_PD -

Reset 0 00000 0 0

Access R/W RRRRRR/WR/W

Table 8. Description of PCON bits

Bit Symbol Description

7 SMOD Serial MODe:

When set to logic 1, the baud rate of the Debug UART is doubled

6 to 3 - Reserved.

1 CPU_PD Power-down:

When set to logic 1, the microcontroller goes in Power-down mode

0 Reserved This bit should only ever contain logic 0.

Table 9. Interrupt vector

Interrupt

number

Interrupt

vector

Interrupt sources Incremental priority level

(conﬂict resolution level)

0 0003h External P32_INT0 Highest

1 000Bh Timer0 interrupt

2 0013h External P33_INT1

3 001Bh Timer1 interrupt

4 0023h Debug UART interrupt

5 002Bh Timer2 interrupt

6 0033h NFC-WI interrupt

7 003Bh LDO overcurrent interrupt

8 0043h Reserved

9 004Bh CIU interrupt 1

10 0053h CIU interrupt 0

11 005Bh I

C interrupt

12 0063h SPI, FIFO, or HSU interrupts

13 006Bh Reserved

14 0073h General Purpose IRQ Lowest

Product data sheet Rev. 3.2 — 3 December 2007 18 of 224

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

CONFIDENTIAL

The 2 following tables describe IE1.

8.1.5.3 Interrupt prioritization: IP0 and IP1 registers

Each interrupt source can be individually programmed to be one of two priority levels by

setting or clearing a bit in the interrupt priority registers IP0 and IP1. If two interrupt

requests of different priority levels are received simultaneously, the request with the high

priority is serviced ﬁrst. On the other hand, if the interrupts are of the same priority,

precedence is resolved by comparing their respective conﬂict resolution levels (see

Table 9 on page 16 for details). The processing of a low priority interrupt can be

interrupted by one with a high priority.

A RETI (Return From Interrupt) instruction jumps to the address immediately succeeding

the point at which the interrupt was serviced. The instruction found at the return address

will be executed, prior to servicing any pending interrupts.

Table 12. Interrupt controller IE1 register (SFR: address E8h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol IE1_7 - IE1_5 IE1_4 IE1_3 IE1_2 - IE1_0

Reset 0 0 000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 13. Description of IE1 bits

Bit Symbol Description

7 IE1_7 General purpose IRQ interrupt enable.

When set to logic 1, enables interrupt function of P34, P35, P50_SCL and P71

according to their respective enable and level control bits. See

Table 19 on

page 20, Table 137 on page 94 and Table 143 on page 96.

6 - Reserved. This bit must be set to logic 0

5 IE1_5 FIFO, SPI and HSU interrupt enable.

When set to logic 1, enables FIFO interrupts, SPI interrupts, HSU interrupt.

In HSU mode, the interrupt is when NSS is at logic 0.

For the FIFO interrupts, see

Table 112 on page 75.

For the SPI interrupts, see Table 122 on page 80.

4 IE1_4 I

C interrupt enable.

When set to logic 1, enables I

C interrupt. See

Table 77 on page 54.

3 IE1_3 CIU interrupt 0 enable.

When set to logic 1, enables CIU interrupt 0: CIU_IRQ_0. See

Table 190 on

page 150.

2 IE1_2 CIU interrupt 1 enable.

When set to logic 1, enables the CIU interrupt 1: CIU_IRQ_1. See

Table 190

on page 150.

1 - Reserved. This bit must be set to logic 0.

0 IE1_0 LDO overcurrent interrupt enable.

When set to logic 1, enables the LDO overcurrent detection interrupt. See

Table 127 on page 87.

Product data sheet Rev. 3.2 — 3 December 2007 20 of 224

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

CONFIDENTIAL

8.1.5.4 General purpose IRQ control

The general purpose interrupts are controlled by register GPIRQ.

NOTE: this is not a standard feature of the 8051.

[1] The bit IE1_7 of register IE1 (see Table 13 on page 18) has also to be set to logic 1 to enable the

corresponding CPU interrupt.

Table 18. GPIRQ register (address 6107h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol gpirq_

level_

P71

gpirq_

level_

P50

gpirq_

level_

P35

gpirq_

level_

P34

gpirq_

enable

_P71

gpirq_

enable_

P50

gpirq_

enable_

P35

gpirq_

enable_

P34

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. Description of GPIRQ bits

Bit Symbol Description

7 gpirq_level_P71 Conﬁgures the polarity of signal on P71 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P71 is set).

When set to logic 0, an interrupt will be generated if P71 is at logic 0.

When set to logic 1, an interrupt will be generated if P71 is at logic 1.

6 gpirq_level_P50 Conﬁgures the polarity of signal on P50 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P50 is set).

When set to logic 0, an interrupt will be generated if P50_SCL is at

logic 0.

When set to logic 1, an interrupt will be generated if P50_SCL is at

logic 1.

5 gpirq_level_P35 Conﬁgures the polarity of signal on P35 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P35 is set).

When set to logic 0, an interrupt will be generated if P35 is at logic 0.

When set to logic 1, an interrupt will be generated if P35 is at logic 1.

4 gpirq_level_P34 Conﬁgures the polarity of signal on P34 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P34 is set).

When set to logic 0, an interrupt will be generated if P34 is at logic 0.

When set to logic 1, an interrupt will be generated if P34 is at logic 1.

Remark: If hide_svdd_sig of the register control_rngpower is set and

gpirq_enable_P34 is also set then this bit will be asserted independently

of the level on the pad P34.

3 gpirq_enable_P71 When set to logic 1, enables pad P71 to generate a GPIRQ interrupt

event.

[1]

2 gpirq_enable_P50 When set to logic 1, enables pad P50_SCL to generate a GPIRQ interrupt

event.

[1]

1 gpirq_enable_P35 When set to logic 1, enables pad P35 to generate a GPIRQ interrupt

event.

[1]

0 gpirq_enable_P34 When set to logic 1, enables pad P34 to generate a GPIRQ interrupt

event.

[1]

剩余223页未读，继续阅读

Willok

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