MPC5634微控制器数据表：低功耗设计与参数详解

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"MPC5634是一款由Freescale Semiconductor生产的微控制器，适用于各种工业和汽车应用。这款芯片提供不同封装选项，包括208MAPBGA、144LQFP、100LQFP和176LQFP，适应不同空间和性能需求。MPC5634在设计上强调低功耗和高性能，具有宽泛的工作温度范围和灵活的电源管理特性。" MPC5634微控制器的主要特点和参数包括： 1. **操作参数**：该芯片可以在0MHz到80MHz的频率范围内工作（加上2%的频率调制可达82MHz），并且能在-40°C至150°C的结温范围内稳定运行，这使得它适合在各种苛刻环境中使用。 2. **低功耗设计**：MPC5634的最大功率损耗仅为400mW，非常适合需要节能的应用。其内部设计考虑了动态电源管理，能够根据需求关闭或激活核心及外围设备，进一步节省能源。 3. **软件控制的时钟门控**：通过软件控制，可以开启或关闭外围设备的时钟，这样在不需要特定功能时可以降低功耗。 4. **低功耗停止模式**：在低功耗停止模式下，所有时钟都会停止，达到极低的待机功耗。 5. **工艺技术**：采用90纳米工艺制造，这有助于实现更高的集成度和更低的功耗。 6. **电源管理**：MPC5634只需要一个5.0V±10%（4.5V至5.25V）的电源，内置稳压器可以提供3.3V和1.2V的核心电源。输入和输出引脚也支持4.5V至5.25V的电压范围。 7. **信号电平和阈值**：芯片的输入/输出引脚遵循35%/65% VDDECMOS开关级别，并带有可选择的滞后，确保了信号的稳定性和抗干扰能力。 8. **封装选项**：提供了四种不同的封装形式，包括17x17mm的208MAPBGA，20x20mm的144LQFP，14x14mm的100LQFP和24x24mm的176LQFP，以满足不同应用场景的空间需求。 MPC5634的这些特性使其成为汽车电子、工业自动化以及其他需要高性能、低功耗和灵活电源管理解决方案的应用的理想选择。设计者可以根据具体项目的需求，选择合适的封装和配置，以优化系统的整体性能和能耗。

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor16

— Designed to address AutoSAR task monitor function

• Software watchdog timer (SWT)

— 32-bit timer

— Clock by system clock or crystal clock

— Can generate either system reset or non-maskable interrupt followed by system reset

— Enabled out of reset

• Enhanced modular I/O system (eMIOS)

— 16 timer channels (up to 14 channels in 144 LQFP)

— 24-bit timer resolution

— Supports a subset of the timer modes found in eMIOS on MPC5554

— 3 selectable time bases plus shared time or angle counter bus from eTPU2

— DMA and interrupt request support

— Motor control capability

• Second-generation enhanced time processor unit (eTPU2)

— Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are

used

— Intelligent co-processor designed for timing control

— High level tools, assembler and compiler available

— 32 channels (each channel has dedicated I/O pin in all packages)

— 24-bit timer resolution

— 14 KB code memory and 3 KB data memory

— Double match and capture on all channels

— Angle clock hardware support

— Shared time or angle counter bus with eMIOS

— DMA and interrupt request support

— Nexus Class 1 debug support

— eTPU2 enhancements

– Counters and channels can run at full system clock speed

– Software watchdog

– Real-time performance monitor

– Instruction set enhancements for smaller more flexible code generation

– Programmable channel mode for customization of channel operation

• Enhanced queued A/D converter (eQADC)

— Two independent on-chip RSD Cyclic ADCs

– 8-, 10-, and 12-bit resolution

– Differential conversions

– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit accuracy at 1 MSample/s

(ADC_CLK = 15 MHz) for differential conversions

– Differential channels include variable gain amplifier for improved dynamic range (1; 2; 4)

– Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics

(200 k; 100 k; low value of 5 k)

– Single-ended signal range from 0 to 5 V

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

– Provides time stamp information when requested

– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)

– Supports both right-justified unsigned and signed formats for conversion results

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor 17

– Temperature sensor to enable measurement of die temperature

– Ability to measure all power supply pins directly

— Automatic application of ADC calibration constants

– Provision of reference voltages (25% VREF

and 75% VREF) for ADC calibration purposes

—Up to 34

input channels available to the two on-chip ADCs

— Four pairs of differential analog input channels

— Full duplex synchronous serial interface to an external device

– Has a free-running clock for use by the external device

– Supports a 26-bit message length

– Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers,

or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are

full

— Parallel Side Interface to communicate with an on-chip companion module

— Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued

conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion is 13 system clocks + 1

ADC clock.)

— eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC

command word. Controlled by two different trigger signals; one to define the rate at which results are generated

and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific

time/angle windows, e.g., engine knock sensor sampling.

— Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform

FIR/IIR filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time

domain filtered result at a given engine angle.

— Priority Based CFIFOs

– Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When

commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served

first.

– Supports software and several hardware trigger modes to arm a particular CFIFO

– Generates interrupt when command coherency is not achieved

— External Hardware Triggers

– Supports rising edge, falling edge, high level and low level triggers

– Supports configurable digital filter

— Supports four external 8-to-1 muxes which can expand the input channel number from 34

to 59

• Two deserial serial peripheral interface modules (DSPI)

—SPI

– Full duplex communication ports with interrupt and DMA request support

– Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)

– Support for queues in RAM

– 6 chip selects, expandable to 64 with external demultiplexers

– Programmable frame size, baud rate, clock delay and clock phase on a per frame basis

– Modified SPI mode for interfacing to peripherals with longer setup time requirements

– LVDS option for output clock and data to allow higher speed communication

— Deserial serial interface (DSI)

– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO

– 32 bits per DSPI module

1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.

2. 176-pin and 208-ball packages.

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor18

– Triggered transfer control and change in data transfer control (for reduced EMI)

– Compatible with Microsecond Bus Version 1.0 downlink

• Two enhanced serial communication interface (eSCI) modules

— UART mode provides NRZ format and half or full duplex interface

— eSCI bit rate up to 1 Mbps

— Advanced error detection, and optional parity generation and detection

— Word length programmable as 8, 9, 12 or 13 bits

— Separately enabled transmitter and receiver

— LIN support

— DMA support

— Interrupt request support

— Programmable clock source: system clock or oscillator clock

— Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0

•Two FlexCAN

— One with 32 message buffers; the second with 64 message buffers

— Full implementation of the CAN protocol specification, Version 2.0B

— Based on and including all existing features of the Freescale TouCAN module

— Programmable acceptance filters

— Short latency time for high priority transmit messages

— Arbitration scheme according to message ID or message buffer number

— Listen only mode capabilities

— Programmable clock source: system clock or oscillator clock

— Message buffers may be configured as mailboxes or as FIFO

• Nexus port controller (NPC)

— Per IEEE-ISTO 5001-2003

— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1

— Read and write access (Nexus class 3 feature that is supported on this device)

– Run-time access of entire memory map

– Calibration

— Support for data value breakpoints / watchpoints

– Run-time access of entire memory map

– Calibration

Table constants calibrated using MMU and internal and external RAM

Scalar constants calibrated using cache line locking

— Configured via the IEEE 1149.1 (JTAG) port

• IEEE 1149.1 JTAG controller (JTAGC)

— IEEE 1149.1-2001 Test Access Port (TAP) interface

— 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

— 5-bit instruction register that supports additional public instructions

— Three test data registers: a bypass register, a boundary scan register, and a device identification register

— Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled

until the next reset

— TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

• On-chip Voltage Regulator for single 5 V supply operation

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor 19

— On-chip regulator 5 V to 3.3 V for internal supplies

— On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic

• Low-power modes

— SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the

PLL) selectively disabled in software

— STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system

clock after a predetermined time

2.3 MPC5634M feature details

2.3.1 e200z335 core

The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction

Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback

(stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.

The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a

Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 3232

Hardware Multiplier array, result feed-forward hardware, and support hardware for division.

Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A

Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated

Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a

supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.

Prefetched instructions are placed into an instruction buffer capable of holding six instructions.

Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the

instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer,

a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated

and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle

to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These

include unconditional branches and conditional branches with condition codes that can be resolved early.

Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching

which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two

clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign

extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow

effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore

operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be

optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.

The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power

Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move,

integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.

Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple

interrupt sources to have unique interrupt handlers invoked with no software overhead.

The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision

floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands,

thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type.

Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are

multi-cycle and are not pipelined.

The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a

full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL)

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor20

in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide

and are used for source and destination operands, thus there is a unified storage model for 3232 MAC operations which

generate greater than 32-bit results.

The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar

and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer

of data to and from the extended 64-bit GPRs. This SPE APU is fully binary compatible with e200z6 SPE APU used in

MPC5554 and MPC5553.

The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power

Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit

instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The classic

Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are

designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.

The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt.

These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely

the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable

Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of

the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt

is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed

to be recoverable (code execution may be resumed from where it stopped).

The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When

Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt

source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.

2.3.2 Crossbar

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The

crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access

a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher

priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher

priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave

port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following

features:

• 3 master ports:

— e200z335 core complex Instruction port

— e200z335 core complex Load/Store port

—eDMA

• 4 slave ports

—FLASH

— calibration bus

—SRAM

— Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM

and SWT)

• 32-bit internal address, 64-bit internal data paths

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