"I2C协议规范 7.0详解及用户手册"

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I2C（Inter-IC或I2C-bus）协议是由飞利浦半导体（现在是NXP半导体）开发的一种简单的双向2线总线，用于有效地进行芯片间控制。这种总线只需要两条线路：一个串行数据线（SDA）和一个串行时钟线（SCL）。通过这两条线路，不同的集成电路（IC）可以进行数据传输和通信。 I2C协议的主要特点包括： 1. 简单：I2C总线协议只需要两条线路，大大减少了硬件复杂度。 2. 双向通信：通过I2C总线，主设备和从设备之间可以进行双向通信，支持主设备向从设备发送命令和数据，并可以接收从设备的响应。 3. 多主机支持：I2C协议支持多个主设备连接到同一条总线上，并通过仲裁机制确保每次只有一个主设备访问总线。 4. 多从设备支持：I2C总线可以连接多个从设备，每个从设备有一个唯一的地址，主设备可以通过地址来选择与哪个从设备进行通信。 5. 多种模式支持：I2C协议定义了多种传输速率和模式，包括标准模式（100 kbit/s）、快速模式（400 kbit/s）、快速模式加强版（1 Mbit/s）、超快模式（3.4 Mbit/s）和高速模式（5 Mbit/s）等，以适应不同设备的要求。 6. 多种设备类型支持：I2C总线可以连接各种类型的设备，包括传感器、存储器、扩展IO芯片、显示屏等。 I2C协议的基本工作原理如下： 1. 启动和停止条件：通信开始前，主设备发送启动条件（SDA从高电平跳变到低电平时，SCL保持高电平），通信结束后，主设备发送停止条件（SDA从低电平跳变到高电平时，SCL保持高电平）。 2. 地址传输：主设备发送一个从设备地址，包括写命令或读命令位，从设备通过地址验证来确定是否响应主设备。 3. 数据传输：主设备通过I2C总线发送数据字节，从设备接收数据字节，并可以返回响应字节。数据传输是以字节为单位进行的。 4. 仲裁机制：当多个主设备同时请求访问总线时，I2C总线上的仲裁机制会自动选择一个主设备，并将其它主设备置于等待状态，确保每次只有一个主设备访问总线。总之，I2C协议是一种简单而灵活的芯片间通信协议，可以在相对简单的硬件环境下实现多主从设备间的双向通信。通过支持不同的传输速率和模式，I2C总线可以适应各种设备的需求，方便连接和控制各种外设。I2C协议在各种应用中广泛使用，包括电子设备、嵌入式系统、通信设备等。

NXP Semiconductors

UM10204

C-bus specification and user manual

CLK

SCL

counter

reset

wait

state

start counting

HIGH period

mbc632

Figure 7. Clock synchronization during the arbitration procedure

When all controllers concerned have counted off their LOW period, the clock line is

released and goes HIGH. There is then no difference between the controller clocks and

the state of the SCL line, and all the controllers start counting their HIGH periods. The

first controller to complete its HIGH period pulls the SCL line LOW again.

In this way, a synchronized SCL clock is generated with its LOW period determined by

the controller with the longest clock LOW period, and its HIGH period determined by the

one with the shortest clock HIGH period.

3.1.8 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more

than one controller is used in the system. Targets are not involved in the arbitration

procedure. A controller may start a transfer only if the bus is free. Two controllers may

generate a START condition within the minimum hold time (t

HD;STA

) of the START

condition which results in a valid START condition on the bus. Arbitration is then required

to determine which controller will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each controller

checks to see if the SDA level matches what it has sent. This process may take many

bits. Two controllers can actually complete an entire transaction without error, as long

as the transmissions are identical. The first time a controller tries to send a HIGH, but

detects that the SDA level is LOW, the controller knows that it has lost the arbitration and

turns off its SDA output driver. The other controller goes on to complete its transaction.

No information is lost during the arbitration process. A controller that loses the arbitration

can generate clock pulses until the end of the byte in which it loses the arbitration and

must restart its transaction when the bus is free.

If a controller also incorporates a target function and it loses arbitration during the

addressing stage, it is possible that the winning controller is trying to address it. The

losing controller must therefore switch over immediately to its target mode.

Figure 8 shows the arbitration procedure for two controllers. More may be involved

depending on how many controllers are connected to the bus. The moment there is a

difference between the internal data level of the controller generating DATA1 and the

actual level on the SDA line, the DATA1 output is switched off. This does not affect the

data transfer initiated by the winning controller.

User manual Rev. 7.0 — 1 October 2021

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NXP Semiconductors

UM10204

C-bus specification and user manual

msc609

DATA 1

DATA 2

SDA

SCL

controller 1 loses arbitration

DATA 1 SDA

Figure 8. Arbitration procedure of two controllers

Since control of the I

C-bus is decided solely on the address and data sent by competing

controllers, there is no central controller, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the

moment when one controller sends a repeated START or a STOP condition while the

other controller is still sending data. In other words, the following combinations result in

an undefined condition:

• Controller 1 sends a repeated START condition and controller 2 sends a data bit.

• Controller 1 sends a STOP condition and controller 2 sends a data bit.

• Controller 1 sends a repeated START condition and controller 2 sends a STOP

condition.

3.1.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction

cannot continue until the line is released HIGH again. Clock stretching is optional and in

fact, most target devices do not include an SCL driver so they are unable to stretch the

clock.

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs

more time to store a received byte or prepare another byte to be transmitted. Targets can

then hold the SCL line LOW after reception and acknowledgment of a byte to force the

controller into a wait state until the target is ready for the next byte transfer in a type of

handshake procedure (see Figure 7).

On the bit level, a device such as a microcontroller with or without limited hardware for

the I

C-bus, can slow down the bus clock by extending each clock LOW period. The

speed of any controller is adapted to the internal operating rate of this device.

In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2).

3.1.10 The target address and R/W bit

Data transfers follow the format shown in Figure 9. After the START condition (S), a

target address is sent. This address is seven bits long followed by an eighth bit which is

a data direction bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates

a request for data (READ) (refer to Figure 10). A data transfer is always terminated by

User manual Rev. 7.0 — 1 October 2021

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NXP Semiconductors

UM10204

C-bus specification and user manual

a STOP condition (P) generated by the controller. However, if a controller still wishes to

communicate on the bus, it can generate a repeated START condition (Sr) and address

another target without first generating a STOP condition. Various combinations of read/

write formats are then possible within such a transfer.

1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STOP

condition

START

condition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

mbc604

Figure 9. A complete data transfer

mbc608

R/W

LSBMSB

target address

Figure 10. The first byte after the START procedure

Possible data transfer formats are:

• Controller-transmitter transmits to target-receiver. The transfer direction is not changed

(see Figure 11). The target receiver acknowledges each byte.

• Controller reads target immediately after first byte (see Figure 12). At the moment of

the first acknowledge, the controller-transmitter becomes a controller-receiver and the

target-receiver becomes a target-transmitter. This first acknowledge is still generated

by the target. The controller generates subsequent acknowledges. The STOP condition

is generated by the controller, which sends a not-acknowledge (A) just before the

STOP condition.

• Combined format (see Figure 13). During a change of direction within a transfer,

the START condition and the target address are both repeated, but with the R/W bit

reversed. If a controller-receiver sends a repeated START condition, it sends a not-

acknowledge (A) just before the repeated START condition.

Notes:

1. Combined formats can be used, for example, to control a serial memory. The internal

memory location must be written during the first data byte. After the START condition

and target address is repeated, data can be transferred.

2. All decisions on auto-increment or decrement of previously accessed memory

locations, etc., are taken by the designer of the device.

3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in

the sequence.

4. I

C-bus compatible devices must reset their bus logic on receipt of a START or

repeated START condition such that they all anticipate the sending of a target

User manual Rev. 7.0 — 1 October 2021

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"I2C协议规范 7.0详解及用户手册"

I2C-bus specification and user manual

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