AD7715：0.0015%精度16位Σ-ΔADC手册

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AD7715手册是一份详细介绍新型16位模数转换器AD7715的重要技术文档，该器件由Analog Devices公司出品，具备高精度和低功耗特性。这款数据转换器的核心特点是： 1. **精度高**：AD7715具有0.0015%的非线性度，这意味着其在转换过程中信号的失真非常小，对于需要高精度测量的应用非常理想。 2. **多种接口兼容**：它支持SPI、QSPI™、MICROWIRE™和DSP（数字信号处理器）等多种接口，这使得它能够在不同的系统架构中灵活集成，提高了设计灵活性。 3. **前端可编程增益**：AD7715提供了四种增益选择（1, 2, 32, 和 128），用户可以根据应用需求调整输入信号的放大程度，扩展了动态范围。 4. **差分输入能力**：设计者可以选择将两个信号作为输入，通过差分模式获取更精确的信号处理效果，适用于对信号噪声敏感的应用。 5. **低功耗设计**：最大工作电流仅为450微安，特别是在3V供电下，这对于电池供电或者电源受限的应用来说，是非常节能的特性。 6. **串行接口**：采用三线接口设计，减少了外部连接线路的数量，简化了电路布局，提高了系统的紧凑性和可靠性。 7. **内置滤波器与更新速度可调**：内部低通滤波器能够平滑输出信号，并且输出更新速度是可编程的，适应不同实时性和噪声抑制需求。 8. **电压兼容性**：AD7715有两种版本，分别是AD7715-3（3V供电）和AD7715-5（5V供电），满足不同工作电压环境的需求。 9. **严格的文档支持与反馈机制**：手册中的信息虽然准确可靠，但用户在使用过程中遇到问题时，Analog Devices提供了技术支持，并鼓励用户提供反馈，以持续改进产品性能。最后，该手册还包含了版权声明和保留所有权利的声明，强调了专利权及商标权益，并提供了联系信息，以便用户获取更多技术帮助或了解最新规格变更。综上，AD7715手册为工程师提供了全面的技术指南，对于在高精度数据采集和处理领域进行设计的人员来说，是一份不可或缺的参考资料。

Data Sheet AD7715

Rev. E | Page 7 of 40

= 3 V to 5 V, DV

= 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to

2.4576 MHz, unless otherwise noted. All specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit Conditions/Comments

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

(1.05 ×

REF

)/GAIN

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

Negative Full-Scale Calibration Limit

−(1.05 ×

REF

)/GAIN

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

Offset Calibration Limit

−(1.05 ×

REF

)/GAIN

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

Input Span

0.8 ×

REF

/GAIN

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

(2.1 × V

REF

)/GAIN V GAIN Is the selected PGA gain (1, 2, 32, or 128)

POWER REQUIREMENTS

Power Supply Voltages

Voltage (AD7715-3) 3 3.6 V For specified performance

Voltage (AD7715-5) 4.75 5.25 V For specified performance

Voltage 3 5.25 V For specified performance

Power Supply Currents

Current

= 3.3 V or 5 V. gain = 1 to 128 (f

CLK IN

= 1 MHz) or

gain = 1 or 2 (f

CLK IN

= 2.4576 MHz)

0.27 mA Typically 0.2 mA; BUF bit of the setup register = 0

0.6 mA

Typically 0.4 mA; BUF bit of the setup register = 1, AV

= 3.3 V or 5 V; gain = 32 or 128 (f

CLK IN

= 2.4576 MHz)

0.5 mA Typically 0.3 mA; BUF bit of the setup register = 0

1.1 mA Typically 0.8 mA; BUF bit of the setup register = 1

Current

Digital inputs = 0 V or DV

; external MCLK IN

0.18 mA Typically 0.15 mA. DV

= 3.3 V. f

CLK IN

= 1 MHz

0.4 mA Typically 0.3 mA. DV

= 5 V. f

CLK IN

= 1 MHz

0.5 mA Typically 0.4 mA. DV

= 3.3 V. f

CLK IN

= 2.4576 MHz

0.8

Typically 0.6 mA. DV

= 5 V. f

CLK IN

= 2.4576 MHz

Power Supply Rejection

Depends on gain

Normal-Mode Power Dissipation

= DV

= 3.3 V; digital inputs = 0 V or DV

; external

MCLK IN

1.5 mW BUF bit = 0. all gains 1 MHz clock

2.65 mW BUF bit = 1. all gains 1 MHz clock

3.3 mW BUF bit = 0. Gain = 32 or 128 @ f

CLK IN

= 2.4576 MHz

5.3 mW BUF bit = 1. Gain = 32 or 128 @ f

CLK IN

= 2.4576 MHz

Normal-Mode Power Dissipation

= DV

= 5 V. digital inputs = 0 V or DV

; external

MCLK IN

3.25 mW BUF bit = 0; all gains 1 MHz clock

5 mW BUF bit = 1; all gains 1 MHz clock

6.5 mW BUF bit = 0; gain = 32 or 128 @ f

CLK IN

= 2.4576 MHz

9.5 mW BUF bit = 1; gain = 32 or 128 @ f

CLK IN

= 2.4576 MHz

Standby (Power-Down) Current

20 µA External MCLK IN = 0 V or DV

. typically 10 µA; V

= 5 V

Standby (Power-Down) Current

10 µA External MCLK IN = 0 V or DV

. typically 5 µA; V

= 3.3 V

After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs

all 0s.

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV

+ 30 mV or go more negative than AGND − 30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV

current and power dissipation will vary depending on the

crystal or resonator type (see the Clocking and Oscillator Circuit section).

Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter

notches of 20 Hz or 60 Hz.

PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.

If the external master clock continues to run in standby mode, the standby current increases to 50 µA typical. When using a crystal or ceramic resonator across the

MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator

type (see the Standby Mode section).

AD7715 Data Sheet

Rev. E | Page 8 of 40

TIMING CHARACTERISTICS

= 3 V to 5.25 V; AV

= 3 V to 5.25 V; AGND = DGND = 0 V; f

CLKIN

= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DV

, unless

otherwise noted.

Table 4.

Parameter

1, 2

Limit at T

MIN

, T

MAX

(A Version)

Unit Conditions/Comments

CLKIN

3, 4

400

kHz min

Master clock frequency: crystal oscillator or externally supplied for specified

performance

2.5 MHz max

CLK IN LO

0.4 × t

CLK IN

ns min Master clock input low time; t

CLK IN

= 1/f

CLK IN

CLK IN HI

0.4 × t

CLK IN

ns min Master clock input high time

500 × t

CLK IN

ns nom

DRDY

high time

100 ns min

RESET

pulsewidth

Read Operation

0 ns min

DRDY

setup time

120 ns min

falling edge to SCLK rising edge setup time

0 ns min SCLK falling edge to data valid delay

ns max

= 5 V

100

ns max

= 3.3 V

100 ns min SCLK high pulsewidth

100 ns min SCLK low pulsewidth

0 ns min

rising edge to SCLK rising edge hold time

10 ns min Bus relinquish time after SCLK rising edge

60 ns max DV

= +5 V

100 ns max DV

= +3.3 V

100 ns max

SCLK falling edge to

DRDY

high

Write Operation

120 ns min

falling edge to SCLK rising edge setup time

30 ns min Data valid to SCLK rising edge setup time

ns min

Data valid to SCLK rising edge hold time

100 ns min SCLK high pulsewidth

100 ns min SCLK low pulsewidth

0 ns min

rising edge to SCLK rising edge hold time

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV

) and timed from a voltage level of 1.6 V.

See Figure 8 and Figure 9.

CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw

higher current than specified and possibly become uncalibrated.

The AD7715 is production tested with f

CLKIN

at 2.4576 MHz (1 MHz for some I

tests). It is guaranteed by characterization to operate at 400 kHz.

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V

or V

limits.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

DRDY

returns high after the first read from the device after an output update. The same data can be read again, if required, while

DRDY

is high although take care that

subsequent reads do not occur close to the next output update.

OUTPUT

+1.6V

SINK

(800µA AT DV

= 5V

100µA AT DV

= 3.3V)

SOURCE

(200µA AT DV

= 5V

100µA AT DV

= 3.3V)

50pF

08519-002

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

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