Cypress CY14E256L：256Kb高速nvSRAM with Quantum Trap Technology

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Cypress Semiconductor Corporation的CYPRESS-CY14E256L是一款高性能的256-Kbit (32Kx8)静态随机存取存储器(SRAM)，专为需要高可靠性和快速访问速度的应用设计。这款产品具有以下关键特性： 1. **访问时间**：CY14E256L提供两种不同的访问时间，即25ns和45ns，这使得它在数据读写操作中表现出高效的性能。 2. **自动存储功能**：在电源关闭时，通过外接68微法（μF）电容，实现了"Hands-off"自动存储（STORE）功能，无需额外的电源管理，确保了数据在断电时能自动保存。 3. **非易失性存储**：嵌入式的量子陷阱技术是其核心亮点，允许用户通过软件、硬件或自动存储(Autostore)在电源关闭时将数据转移到高可靠性量子陷阱单元，提供了极高的数据持久性。 4. **数据恢复与重写**：当需要时，用户可以通过软件或设备上电来执行召回(RECALL)操作，将量子陷阱中的数据回传到SRAM中，支持无限次的读写循环。 5. **低功耗与快速响应**：15毫安（mA）典型电流消耗配合200ns的IC周期时间，确保了低功耗的同时，也保持了快速的数据处理能力。 6. **高耐用性**：CY14E256L可以承受高达1,000,000次的STORE循环，保证了至少100年的数据保留期，即使在极端条件下也能保持数据安全。 7. **供电需求**：该器件仅需单个5V电源，且工作范围可以扩展至+10%，适用于商业环境中的多种应用。 8. **封装形式**：采用小外形集成电路（SOIC）封装，紧凑的尺寸便于集成到各种电路板设计中。 9. **环保合规**：CYPRESS-CY14E256L符合RoHS（限制有害物质指令）标准，符合当前电子产品的环保要求。 CYPRESS-CY14E256L是一款集快速、稳定和高可靠性于一身的存储解决方案，适用于对数据持久性和低功耗有严格要求的应用场景，如工业控制、嵌入式系统和便携设备等。它的设计充分考虑了现代电子产品的各种需求，确保了长时间的运行和数据保护。

PRELIMINARY

CY14E256L

Document #: 001-06968 Rev. *C Page 4 of 16

In system power mode (Figure 2), both V

and V

CAP

are

connected to the +5V power supply without the 68-µF

capacitor. In this mode the AutoStore function of the

CY14E256L will operate on the stored system charge as

power goes down. The user must, however, guarantee that

does not drop below 3.6V during the 10-ms STORE cycle.

If an automatic STORE on power loss is not required, then V

can be tied to ground and + 5V applied to V

CAP

(Figure 3). This

is the AutoStore Inhibit mode, in which the AutoStore function

is disabled. If the CY14E256L is operated in this configuration,

references to V

should be changed to V

CAP

throughout this

data sheet. In this mode, STORE

operations may be triggered

through software control or the HSB

pin. It is not permissible

to change between these three options “on the fly”.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware Store operations will be ignored unless at least one

WRITE operation has taken place since the most recent

STORE or RECALL cycle. Software initiated STORE cycles

are performed regardless of whether a WRITE operation has

taken place. The HSB

signal can be monitored by the system

to detect an AutoStore cycle is in progress. (In the above

Figures 1, 2 and 3 * indicates that If HSB is not used, it should

be left unconnected.)

Hardware STORE (HSB) Operation

The CY14E256L provides the HSB pin for controlling and

acknowledging the STORE operations. The HSB

pin can be

used to request a hardware STORE cycle. When the HSB

is driven low, the CY14E256L will conditionally initiate a

STORE operation after t

DELAY

. An actual STORE cycle will

only begin if a WRITE to the SRAM took place since the last

STORE or RECALL cycle. The HSB

pin also acts as an

open-drain driver that is internally driven low to indicate a busy

condition while the STORE (initiated by any means) is in

progress.

SRAM READ and WRITE operations that are in progress

when HSB

is driven low by any means are given time to

complete before the STORE operation is initiated. After HSB

goes low, the CY14E256L will continue SRAM operations for

DELAY

. During t

DELAY

, multiple SRAM READ operations may

take place. If a WRITE is in progress when HSB

is pulled low

it will be allowed a time, t

DELAY

, to complete. However, any

SRAM WRITE cycles requested after HSB

goes low will be

inhibited until HSB

returns high.

The HSB pin can be used to synchronize multiple CY14E256L

while using a single larger capacitor. To operate in this mode

the HSB pin should be connected together to the HSB pins

from the other CY14E256L. An external pull-up resistor to +5V

is required since HSB

acts as an open-drain pull-down. The

CAP

pins from the other CY14E256L parts can be tied

together and share a single capacitor. The capacitor size must

be scaled by the number of devices connected to it. When any

one of the CY14E256L detects a power loss and asserts HSB

the common HSB

pin will cause all parts to request a STORE

cycle (a STORE

will take place in those CY14E256L that have

been written since the last nonvolatile cycle).

During any STORE operation, regardless of how it was

initiated, the CY14E256L will continue to drive the HSB

low, releasing it only when the STORE is complete. Upon

completion of the STORE operation the CY14E256L will

remain disabled until the HSB

pin returns high.

If HSB is not used, it should be left unconnected.

Hardware RECALL (Power-up)

During power-up, or after any low-power condition (V

SWITCH

), an internal RECALL request will be latched. When

once again exceeds the sense voltage of V

SWITCH

, a

RECALL cycle will automatically be initiated and will take

HRECALL

to complete.

If the CY14E256L is in a WRITE

state at the end of power-up

RECALL, the SRAM

data will be corrupted. To help avoid this

situation, a 10-Kohm resistor should be connected either

between WE and system V

or between CE and system V

Software STORE

Data can be transferred from the SRAM to the nonvolatile

memory by a software address sequence. The CY14E256L

software STORE cycle is initiated by executing sequential

-controlled READ cycles from six specific address locations

in exact order. During the STORE cycle an erase of the

previous nonvolatile data is first performed, followed by a

program of the nonvolatile elements. Once a STORE cycle is

initiated, further input and output are disabled until the cycle is

completed.

Because a sequence of READs from specific addresses is

used for STORE initiation, it is important that no other READ

or WRITE accesses intervene in the sequence, or the

sequence will be aborted and no STORE or RECALL will take

place.

To initiate the software STORE cycle, the following READ

sequence must be performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

Figure 3. AutoStore Inhibit Mode

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