STM32F756xx：高性能Cortex-M7 MCU，集成FPU与丰富外设

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"STM32F756xx是基于ARM Cortex-M7内核的32位微控制器，配备浮点单元（FPU），最高可达1MB的闪存和320+16+4KB RAM，包括加密功能、USB OTG HS/FS、以太网、18个定时器、3个ADC、25个通信接口、摄像头和LCD支持。它还具有适应性实时加速器（ART Accelerator）和L1缓存，以实现零等待状态执行。" STM32F756系列是STMicroelectronics推出的一款高性能微控制器，主要针对嵌入式应用，特别是对处理能力和实时性能有高要求的场合。该系列微控制器的关键特性如下： 1. **核心处理器**: 采用32位ARM Cortex-M7内核，集成浮点单元（FPU），可提供高达428DMIPS的运算性能，支持2.14DMIPS/MHz的Dhrystone 2.1基准测试。此外，还包含了一个适应性实时加速器（ART Accelerator）和4KB的数据及指令缓存，使得从嵌入式Flash或外部内存执行时无需等待状态。 2. **内存配置**: 提供最多1MB的闪存存储空间，用于程序代码和数据存储。内含320KB SRAM，其中64KB为数据TCM RAM，用于关键实时数据；16KB为指令TCM RAM，用于关键实时程序；以及4KB的备份SRAM，即使在低功耗模式下也能保持可用。 3. **扩展存储控制器**: 支持灵活的外部存储器控制器，可以连接最高32位数据总线的SRAM、PSRAM、SDRAM/LPSDRSDRAM以及NOR/NAND等不同类型的内存。 4. **通信接口**: 集成了多种通信接口，包括USB OTG高速/全速接口，以太网接口，以及多达25个不同的通信接口，为系统扩展提供了广泛的支持。 5. **外围设备**: 包括双模式Quad SPI接口，用于高速串行通信；8080/6800模式的LCD并行接口，支持多种显示设备；以及LCD-TFT控制器，可支持最高XGA分辨率的显示，并配备专用的Chrom-ART Accelerator，提升图形处理性能。 6. **模拟特性**: 3个ADC（模数转换器）为系统提供了丰富的模拟输入能力，对于传感器和其他模拟信号的处理至关重要。 7. **电源管理与低功耗**: 设计了多种低功耗模式，确保在不同工作场景下的高效能与节能。 STM32F756系列的这些特性使其适用于多种应用领域，如工业控制、消费电子、医疗设备、物联网节点、智能家居以及高级人机交互界面等。开发人员可以利用其强大的计算能力和丰富的外设接口，设计出复杂且高效的嵌入式解决方案。

Functional overview STM32F756xx

16/111 DocID026379 Rev 1

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

2.9 Quad SPI memory interface (QUADSPI)

All STM32F75xx devices embed a Quad SPI memory interface, which is a specialized

communication interface targetting Single, Dual or Quad SPI flash memories. It can work in:

• Direct mode through registers

• External flash status register polling mode

• Memory mapped mode.

Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.

Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in

Single Data Rate or Dual Data Rate.

2.10 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)

and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

XGA (1024x768) resolution with the following features:

• 2 displays layers with dedicated FIFO (64x32-bit)

• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

• Up to 8 Input color formats selectable per layer

• Flexible blending between two layers using alpha value (per pixel or constant)

• Flexible programmable parameters for each layer

• Color keying (transparency color)

• Up to 4 programmable interrupt events.

2.11 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

• Rectangle filling with a fixed color

• Rectangle copy

• Rectangle copy with pixel format conversion

• Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables.

DocID026379 Rev 1 17/111

STM32F756xx Functional overview

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

2.12 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M7 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

2.13 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected

to the 16 external interrupt lines.

2.14 Clocks and startup

On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can

then select as system clock either the RC oscillator or an external 4-26 MHz clock source.

This clock can be monitored for failure. If a failure is detected, the system automatically

switches back to the internal RC oscillator and a software interrupt is generated (if enabled).

This clock source is input to a PLL thus allowing to increase the frequency up to 200 MHz.

Similarly, full interrupt management of the PLL clock entry is available when necessary (for

example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 200 MHz while the maximum frequency of the high-speed APB domains is

100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.

The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio

class performance. In this case, the I

S and SAI master clock can generate all standard

sampling frequencies from 8 kHz to 192 kHz.

Functional overview STM32F756xx

18/111 DocID026379 Rev 1

2.15 Boot modes

At startup, the boot memory space is selected by the BOOT0 pin and BOOT_ADDx option

bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF

which includes:

• All Flash address space mapped on ITCM or AXIM interface

• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface

• The System memory bootloader

The boot loader is located in system memory. It is used to reprogram the Flash memory

through a serial interface.

2.16 Power supply schemes

• V

= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through V

pins.

• V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

• VDDUSB can be connected either to VDD or an external independent power supply

(3.0 to 3.6V) for USB transceivers. For example, when device is powered at 1.8V, an

independent power supply 3.3V can be connected to VDDUSB.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

Note: V

DDA

minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 2.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode

versus device operating mode to identify the packages supporting this option.

2.17 Power supply supervisor

2.17.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On the other packages, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default BOR

thresholds, or to disable BOR permanently. Three BOR thresholds are available through

option bytes. The device remains in reset mode when V

is below a specified threshold,

POR/PDR

or V

BOR

, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors

the V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

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