MDIN200 VGA开发手册：视频处理与驱动指南

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"MDIN200_datasheet_v0.4.pdf——这是一款VGA的开发手册，可作为视频处理驱动开发的指导手册，标签包括mdin和vga。" MDIN-200是一款由Macro Image Technology, Inc.推出的第四代SD到全高清上转换器。这款芯片专为视频处理和驱动开发设计，特别是在VGA显示技术领域具有重要的应用价值。该数据手册是开发人员进行相关工作的重要参考资料。 MDIN-200的特点和功能包括： 1. 高度集成：MDIN-200是一款单芯片解决方案，集成了去交织和格式转换功能。这意味着它可以处理不同类型的视频信号，无论是逐行扫描还是隔行扫描，都能轻松应对。 2. 10位精度的数字视频输入：支持10位颜色组件精度的数字视频输入，确保了高画质的视频处理。这在处理高清内容时尤其重要，因为它能提供更丰富的色彩层次和细节。 3. 多样化的输入和输出接口：MDIN-200提供可配置的数字视频输入端口，适应不同类型的视频源。同时，它还具备模拟组件输出端口和数字输出端口，专用于输出逐行扫描类型的视频信号，适用于各种显示设备。 4. 法律声明：文档受到版权保护，未经Macro Image Technology, Inc.的书面同意，禁止复制、分发或公开展示此文档。此外，文档内容可能在未通知的情况下发生变化，使用者应保持对最新版本的关注。 5. 保密性：MDIN-200的数据手册被标记为Macro Image Technology, Inc.的机密资料，表明其技术细节和规格可能包含公司的核心技术信息。这款开发手册将帮助工程师理解和利用MDIN-200的特性，进行VGA视频处理和驱动程序的开发。对于需要处理高清视频信号，或者需要进行格式转换的项目来说，MDIN-200提供了强大的硬件支持。通过详细阅读和理解手册中的技术参数和操作指南，开发人员可以优化系统性能，实现高效的视频处理流程。

MDIN-200

Datasheet Version 0.4

Macro Image Technology, Inc. Confidential

2.2 Output Port Pin Mapping

MDIN-200 has configurable digital output pins as shown in Table 2-2. The output port pin maping is

determined by digital_out_format and digital_8bit_out_en of the register out_control (address 0x4A2).

Mode

Pin Name

RGB 4:4:4

8-bit

YCbCr

4:4:4

8-bit

YC 4:2:2

10-bit

YC 4:2:2

8-bit

YC-muxed

10-bit

YC-muxed

8-bit

DATA_OUT0 B0 Cb0 - - - -

DATA_OUT1 B1 Cb1 - - - -

DATA_OUT2 B2 Cb2 Y0 - YC0 -

DATA_OUT3 B3 Cb3 Y1 - YC1 -

DATA_OUT4 B4 Cb4 - - - -

DATA_OUT5 B5 Cb5 - - - -

DATA_OUT6 B6 Cb6 C0 - - -

DATA_OUT7 B7 Cb7 C1 - - -

DATA_OUT8 G0 Y0 Y2 Y0 YC2 YC0

DATA_OUT9 G1 Y1 Y3 Y1 YC3 YC1

DATA_OUT10 G2 Y2 Y4 Y2 YC4 YC2

DATA_OUT11 G3 Y3 Y5 Y3 YC5 YC3

DATA_OUT12 G4 Y4 Y6 Y4 YC6 YC4

DATA_OUT13 G5 Y5 Y7 Y5 YC7 YC5

DATA_OUT14 G6 Y6 Y8 Y6 YC8 YC6

DATA_OUT15 G7 Y7 Y9 Y7 YC9 YC7

DATA_OUT16 R0 Cr0 C2 C0 - -

DATA_OUT17 R1 Cr1 C3 C1 - -

DATA_OUT18 R2 Cr2 C4 C2 - -

DATA_OUT19 R3 Cr3 C5 C3 - -

DATA_OUT20 R4 Cr4 C6 C4 - -

DATA_OUT21 R5 Cr5 C7 C5 - -

DATA_OUT22 R6 Cr6 C8 C6 - -

DATA_OUT23 R7 Cr7 C9 C7 - -

digital_out_format

‘00’ ‘00’ ‘01’ ‘01’ ‘10’ ‘10’

digital_8bit_out_en

don’t care don’t care ‘0’ ‘1’ ‘0’ ‘1’

Table 2-2. Output Port Pin Mapping

2.3 Active Window Size and Position of Input Video

MDIN-200 can be programmed to define the size and position of the received video by register setttings. It is necessary

to adjust active window size and position of input video when horizontal and vertical timing signals received through input

port A are sync signal, not active signal. In this case, the function of adjusting size and position that MDIN-200 provides is

very helpful to extract the desired active video data without glue logic within a system. Figure 2-1 shows how this function

works. The horizontal size is determined by in_size_h register, and the result is the minimum value between the register

value and duration of the received horizontal sync signal. The vertical size is determined by in_size_v register, and the

result is the minimum value between the register value and duration of the received vertical sync signal. The offset of

horizontal position is determined by in_hact_offset register. As a result, active window is shifted by the register value.

The offset of vertical position is also controlled as that of horizontal position by in_vact_offset register.

MDIN-200

Datasheet Version 0.4

Macro Image Technology, Inc. Confidential

control register for preprocessing of video data value. The coefficient registers of csc_f_coef0, csc_f_coef1, …,

csc_f_coef7 and csc_f_coef8 in the input block are user programmable. All input components and output components

can be added or substracted by setting csc_f_offset_y, csc_f_offset_cb, csc_f_offset_cr, csc_f_offset_g,

csc_f_offset_b and csc_f_offset_r registers as user defined values. And it is possible to make the input and output

value clipped to a certain range. One way is clipping for Cb, Cr, B, R to be ranging from 0 to 1023 and the other is from -

512 to 511. User can select each clipping mode for each Cb, Cr, B, R. And Y and G signals are clipped to be ranging

from 0 to 1023. The CSC can be bypassed by setting csc_f_bypass bit of csc_f_control register. All the coefficient and

offset registers are 12-bit 2’s complement values, and 512 corresponds to 1.0 (unity).

The register values in the following example can be used to convert RGB video to the ITU-R BT.601 YCbCr format. The

RGB and YCbCr data are assumed a range of 0 to 1023. If the range is 64 to 940, the coefficient and offset registers

should be adjusted properly.

0.511

0.083

0.428

R0.172B0.511G0.339Cb

0.299

0.114

0.587

×+×−×−=

×−×+×−=

csc_f_coef0 = 0x12D, csc_f_coef1 = 0x03A, csc_f_coef2 = 0x099

csc_f_coef3 = 0xF52, csc_f_coef4 = 0x106, csc_f_coef5 = 0xFA8

csc_f_coef6 = 0xF25, csc_f_coef7 = 0xFD6, csc_f_coef8 = 0x106

csc_f_offset_g = 0x000, csc_f_offset_b = 0x000, csc_f_offset_r = 0x000

csc_f_offset_y = 0x000, csc_f_offset_cb = 0x200, csc_f_offset_cr = 0x200

csc_f_control = 0x1F8

2.5 Auto Detection and Compensation of Input Video Sync

MDIN-200 provides input auto detection capability. Auto detection of the follwing parameters is supported - horizontal

sync period, horizontal size or the number of horizontal pixels for both the high and low period of horizontal sync, vertical

size or the number of vertical lines for both high and low period of vertical sync, and scan type. Auto detection on the

input port B is not necessary since it always receives video data with embedded timing references.

MDIN-200 also detects the existence of video sync signal and the change in the horizontal and vertical sync period. Auto

detection of sync existence or sync change is always performed and the other auto detection features are performed by

setting in_detect_en register. The results of auto detection are stored in input status registers (in_sync_lost, in_hsync,

in_scan_i, in_hsync_high, in_hsync_low, in_vsync_high, in_vsync_low) and they can be read and used by an

external host processor for the detection of exact input video format.

MDIN-200 supports composite sync input. It can extract the hsync and vsync from the composite sync signal which can

be obtained by slicing the bi-level or tri-level sync tips of the input video signal. MDIN-200 can receive a composite sync

signal through HACTIVE_A pin by setting in_sync_ctrl register.

And MDIN-200 can extract the sync information even though the input sync signals are in non-standard format. When the

timing of vsync-transition to hsync is different from the standard timing it can be compensated by setting

vsync_forced_rising_a register. In this case, the horizontal total size of input signal needs to be specified in

in_fieldid_ctrl register. And as prevention against unstable vsync-rising, the internal vsync signal can be forced to rise at

any position by setting vsync_forced_rising_a register. in_sync_sel register determines which input sync will be

selected between the original and compensated input sync signals.

2.6 Front Noise Reduction Filter

MDIN-200 has two blocks to perform noise reduction function. The first block is the front noise reduction filter and the

second block is the post noise reduction during deinterlacing process, i.e. 3D noise reduction. The front noise reduction

filter is a one dimensional filter for input video signal. Its characteristics are programmable. The information from this filter

is also used in deinterlacing process. The front noise reduction filter has two types of filter - median filter and FIR low

pass filter. The median filter has 3 taps and the FIR low pass filter has 15 taps and the coefficients are programmable.

The difference between input and output of the median filter is stored in median_flt_difference register and the

difference between input and output of the FIR low pass filter is stored in nr_flt_difference register. The difference

valuses are used in post noise reduction of deinterlacing process to reduce artifacts caused by noise, and user can

select which result to be used by setting noise_reduction_flt_diff_sel register. This front noise reduction filter,

alternatively, can be used as anti-aliasing filter. When the input video is scaled down in the horizontal direction this filter

MDIN-200

Datasheet Version 0.4

Macro Image Technology, Inc. Confidential

control registers properly. The sync control mode is selected by sync_ctrl register. The timings of output sync signals are

fully user-programmable by setting htotal_size, hactive_start, hactive_end, hsync_start, hsync_end, vactive_start,

vactive_end, vsync_start, vsync_end registers. The polarities of all output sync signals are programmable and the

composite sync is also supported. Figure 2-3 shows the details of output sync generation. The value of hsync_total

2.8 Deinterlace

MDIN-200 provides deinterlacing function for interlaced input video. It supports 3-D motion adaptive deinterlacing of

standard deifinition videos such as 480i or 576i. The supported maximum horizontal size is 1024 pixels for 8-bit pixel

precision mode and 768 pixels for 10-bit pixel precision mode.

2.8.1 Motion Adaptive Deinterlace

MDIN-200 uses 6 fields of frame memory to get motion information and performs motion-adaptive interpolation. MDIN-

200 supports three kinds of deinterlacing modes - intra-only mode, inter-only mode and adaptive mode. The intra-only

mode of deinterlacing uses only current field to calculate and generate the deinterlaced pixel output (known as bob

mode). The inter-only mode of deinterlacing always generates the deinterlaced pixel output by inter-interpolation using

current field and previous field (known as weave mode). The adaptive mode performs deinterlacing using weighted

combination of intra-field interpolation and inter-field interpolation on a per pixel basis. MDIN-200 detects motion

information using 6 fields so that the motion detection errors will be minimized.

2.8.2 Edge Preserving

MDIN-200 provides high quality deinterlacing with detecting and preserving edges of various angles when the intra-field

interpolation should be used. If a simple deinterlacing algorithm that does not support edge preservation is used, there

should be much jagged edges on the output video after deinterlacing. MDIN-200 uses a proprietary algorithm in detecting

the existence and direction of edges for interlaced input video, and it performs deinterlacing according to the edge

detection results so that a smooth and graceful deinterlaced result will be provided. MDIN-200 also detects the frequency

characteristics of the video area to deinterlace and uses them to determine the edge direction. So the artifacts for high

frequency area in the video can be minimized.

2.8.3 Fast Motion Detect and Handling

MDIN-200 supports graceful deinterlacing for interlaced input video with fast motion. If a deinterlacing algorithm that

supports motion-adaptive deinterlacing without fast motion support, there must be artifacts of undesired inter-field

interpolation. MDIN-200 detects fast motion using 6 fields of frame memory and the motion information of the recent 30

fields and perfoms appropriate deinterlacing algorithm to remove those artifacts.

2.8.4 Motion Boundary Preserving

There can be a still object on the moving area in the scene. The boundary of this object is hard to be preserved due to

the surrounding motions. MDIN-200 can detect the motion boundary and preserve it even though the object has one line

size in vertical direction. For this operation MDIN-200 uses motion information of recent 30 fields.

2.8.5 Film Mode and Bad Edit Detection

MDIN-200 supports film mode detection and proper processing to deinterlace the video from film source without artifacts.

In a normally interlaced video, successive fields are captured at different time instances so that they have different

pictures if the objects in the video are moving. But when film of 24Hz or 30Hz frame rate is converted to an interlaced

video, 2 or 3 successive fields may be captured from one film frame due to 3:2 or 2:2 pull-down processing of telecine

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