ADS8584S: 16位高速四通道同时采样ADC技术资料

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"ADS8584S 是一款16位高速、四通道同步采样模数转换器(ADC)，由德州仪器(Texas Instruments)生产。该器件具有高精度和快速转换能力，适用于多种数据采集系统。ADS8584S 设计中包含了模拟输入、参考电压、电源、数字接口和控制信号等关键组件。" ADS8584S 是一个16位的SAR（逐次逼近寄存器）ADC，提供四个独立的模拟输入通道，分别为AIN_1P, AIN_1GND, AIN_2P, AIN_2GND, AIN_3P, AIN_3GND, AIN_4P 和 AIN_4GND，这些通道可以同时进行采样，提高了系统的数据吞吐率。每个通道都配备了PGA（可编程增益放大器），可以根据应用需求调整输入信号的放大倍数。该器件内置了一个2.5V的内部参考电压源（2.5VREF），也可以通过REFIN/REFOUT 引脚外部提供参考电压。REFCAPA 和 REFCAPB 引脚用于稳定参考电压，REFSEL 控制选择内部或外部参考。模拟电源分别由AVDD 和 AGND 提供，而数字部分由DVDD 供电。在数字接口方面，ADS8584S 支持串行（SER/PAR）和并行（PAR/SER）数据传输，通过DB[15:0] 输出转换结果。DOUTA 和 DOUTB 用于并行模式的数据输出。此外，CONVSTA 和 CONVSTB 控制转换开始，RD/SCLK 作为串行时钟，CS（片选）用于器件选择，RESET 用于复位ADC，而STBY 用于使能或关闭ADC。FRSTDATA 标志第一个数据转换完成，BUSY 指示ADC正在进行转换。 ADS8584S 还包括数字滤波功能，能够减少噪声和改善信号质量。1M: Clamp 和 1M: 3rd-Order LPF Clamp 代表了一阶和三阶低通滤波器，用于进一步平滑输出数据。同时，每个通道都有一个PGA ADC 驱动器，以优化信号处理性能。在安全性和使用注意事项上，用户需注意此器件的使用可能涉及到知识产权问题，并且不应用于关键的安全应用中，除非符合特定的安全标准。此外，数据手册中的一个重要通知强调了器件的可用性、保修、变更及免责声明。 ADS8584S 是一款高性能的四通道ADC，适用于需要高速、高分辨率模拟到数字转换的系统，如工业自动化、测试与测量、医疗设备等领域。其丰富的功能集和灵活的接口使其在各种应用中具有广泛的应用潜力。

ADS8584S

SBAS834A –APRIL 2017–REVISED APRIL 2017

www.ti.com

Product Folder Links: ADS8584S

7.6 Timing Requirements: CONVST Control

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 330 kSPS

(unless otherwise noted) (see Figure 1)

MIN NOM MAX UNIT

ACQ

Acquisition time:

BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB

1 µs

PH_CN

CONVSTA, CONVSTB pulse high time 25 ns

PL_CN

CONVSTA, CONVSTB pulse low time 25 ns

SU_BSYCS

Setup time: BUSY falling to CS falling 0 ns

SU_RSTCN

Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB 25 ns

PH_RST

RESET pulse high time 50 ns

D_CNAB

Delay between rising edges of CONVSTA and CONVSTB 500 µs

7.7 Timing Requirements: Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 330 kSPS

(unless otherwise noted) (see Figure 2)

MIN NOM MAX UNIT

DZ_CNCS

Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of

data read operation during conversion

10 ns

DZ_CSBSY

Delay between CS rising edge to BUSY falling edge, end of data read

operation during conversion

40 ns

SU_BSYCS

Setup time: BUSY falling edge to CS falling edge, start of data read operation

after conversion

0 ns

D_CSCN

Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of

data read operation after conversion

10 ns

7.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 330 kSPS (unless otherwise noted) (see Figure 3)

MIN NOM MAX UNIT

PH_CS

PH_RD

CS and RD high time 15 ns

PL_CS

PL_RD

CS and RD low time 15 ns

HT_RDDB

HT_CSDB

Hold time: RD and CS rising edge to DB[15:0] invalid 2.5 ns

ADS8584S

www.ti.com

SBAS834A –APRIL 2017–REVISED APRIL 2017

Product Folder Links: ADS8584S

7.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 330 kSPS (unless otherwise noted) (see Figure 4)

MIN NOM MAX UNIT

SU_CSRD

Setup time: CS falling edge to RD falling edge 0 ns

HT_RDCS

Hold time: RD rising edge to CS rising edge 0 ns

PL_RD

RD low time 15 ns

PH_RD

RD high time 15 ns

HT_CSDB

Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns

HT_RDDB

Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

7.10 Timing Requirements: Serial Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V

and V

at datasheet

limits, and f

SAMPLE

= 330 kSPS (unless otherwise noted) (see Figure 5)

MIN NOM MAX UNIT

SCLK

SCLK time period 50 ns

PH_SCLK

SCLK high time 0.45 0.55 t

SCLK

PL_SCLK

SCLK low time 0.45 0.55 t

SCLK

HT_CKDO

Hold time: SCLK rising edge to DOUTA, DOUTB invalid 7 ns

SU_CSCK

Setup time: CS falling to first SCLK edge 8 ns

HT_CKCS

Hold time: last SCLK active edge to CS high 10 ns

7.11 Timing Requirements: Byte Mode Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits, and

SAMPLE

= 330 kSPS (unless otherwise noted) (see Figure 6)

MIN NOM MAX UNIT

SU_CSRD

Setup time: CS falling edge to RD falling edge 0 ns

HT_RDCS

Hold time: RD rising edge to CS rising edge 0 ns

PL_RD

RD low time 15 ns

PH_RD

RD high time 15 ns

HT_CSDB

Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns

HT_RDDB

Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

7.12 Timing Requirements: Oversampling Mode

MIN NOM MAX UNIT

HT_OS

Hold time: BUSY falling to OSx 20 ns

SU_OS

Setup time: BUSY falling to OSx 20 ns

(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

7.13 Timing Requirements: Exit Standby Mode

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C, AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), V

and V

at datasheet limits, and f

SAMPLE

= 330 kSPS (unless otherwise

noted) (see Figure 8)

MIN NOM MAX UNIT

D_STBYCN

Delay between STBY rising edge to CONVSTA or CONVSTB rising edge

(1)

100 µs

ADS8584S

SBAS834A –APRIL 2017–REVISED APRIL 2017

www.ti.com

Product Folder Links: ADS8584S

(1) Excludes wake-up time for external reference device.

7.14 Timing Requirements: Exit Shutdown Mode

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), V

and V

at datasheet limits, and f

SAMPLE

= 330 kSPS (unless otherwise

noted) (see Figure 9)

MIN NOM MAX UNIT

D_SDRST

Delay between STBY rising edge to RESET rising edge

Internal reference mode 50

External reference mode

(1)

PH_RST

RESET high time 50 ns

D_RSTCN

Delay between RESET falling edge to CONVSTA or CONVSTB rising edge 25 µs

7.15 Switching Characteristics: CONVST Control

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 330 kSPS

(unless otherwise noted) (see Figure 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CYC

ADC cycle time period

No oversampling, parallel read, serial

read with both DOUTA and DOUTB

during conversion

µs

No oversampling, serial read after

conversion with both DOUTA and

DOUTB

3.8

No oversampling, serial read after

conversion with only DOUTA or

DOUTB

5.5

CONV

Conversion time: BUSY high time

No oversampling 2

µs

Oversampling by 2 5

Oversampling by 4 11

Oversampling by 8 23

Oversampling by 16 47

Oversampling by 32 95

Oversampling by 64 191

D_CNBSY

Delay between trailing rising edges of

CONVSTA or CONVSTB and BUSY

rising

15 ns

7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 330 kSPS (unless otherwise noted) (see Figure 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

D_CSDB

Delay time: CS falling edge to DB[15:0]

becoming valid

(out of tri-state)

12 ns

D_RDDB

Delay time: RD falling edge to new

data on DB[15:0]

17 ns

D_CSFD

D_RDFD

Delay time: CS and RD falling edge to

FRSTDATA going high or low out of tri-

state

10 ns

DHZ_CSDB

DHZ_RDDB

Delay time: CS and RD rising edge to

DB[15:0] tri-state

12 ns

DHZ_CSFD

DHZ_RDFD

Delay time: CS and RD rising edge to

FRSTDATA tri-state

10 ns

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