2 FUNDAMENTALS UNIX 6th Edition Commentary
Each pair of registers controls the mapping of
one page i.e. one eighth part of the virtual address
space which 8K bytes (4K words).
Each page may be regarded as an aggregate of
128 blocks, each of 64 bytes (32 words). This latter
size is the “grain size” for the memory mapping
function, and as a practical consequence, it is also
the “grain size” for memory allocation.
Any virtual address belongs to one page or
other. The corresponding physical address is gener-
ated by adding the relative address within the page
to the contents of the corresponding PAR to form
an extended address (18 bits on the PDP11/40 and
11/45; 22 bits on the 11/70).
Thus each page address register acts as a relo-
cation register for one page.
Each page can be divided on a 32 word bound-
ary into two parts, an upper part and lower part.
Each such part has a size which is a multiple of 32
words. In particular one part may be null, in which
case the other part coincides with the whole page.
One of the two parts is deemed to contain valid
virtual addresses. Addresses in the remaining part
are declared invalid. Any attempt to reference an
invalid address will be trapped by the hardware.
The advantage of this scheme is that space in the
physical memory need only be allocated for the
valid r)art of a page.
2.9 Page Description Register
The page description register defines:
(a) the size of the lower part of the page. (The
number stored is actually the number of 32
word blocks less one);
(b) a bit which is set when the upper part is the
valid part. (Also known as the “expansion
direction” bit);
(c) access mode bits defining “no access” or “read
only access” or “read/write access”.
Note that if the valid part is null, this fact must
be shown by setting the access bits to “no access”.
2.10 Memory Allocation
The hardware does not dictate the way areas in
physical memory which correspond to the valid
parts of pages should be allocated (except to the
extent that they must begin and end on a 32 word
boundary). These areas may be allocated in any
order and may overlap to any extent.
In practice the allocation of areas of physical
memory is much more disciplined as we shall see
in Chapter Seven. Areas for pages which are re-
lated are most often allocated contiguously and in
the order of their page numbers, so that all the
segment areas associated with a single program are
contained within one or at most two large areas of
physical memory.
2.11 Memory Management Status Reg-
isters
In addition to the segmentation registers, on the
PDP11/40 there are two memory management sta-
tus registers:
SR0 contains abort error flags and other essential
information for the operating system. In par-
ticular memory management is enabled when
bit 0 of SR0 is on;
SR2 is loaded with the 16 bit virtual address at
the beginning of each instruction fetch.
2.12 “i” and “d” Spaces
In the PDP11/45 and 11/70 systems, there are ad-
ditional sets of segmentation registers. Addresses
created using the pc register (r7) are said to belong
to “i” space, and are translated by a different set of
segmentation registers from those used for the re-
maining addresses which are said to belong to “d”
space.
The advantage of this arrangement is that both
“i” and “d” spaces may occupy up to 32K words,
thus allowing the maximum space which can be al-
located to a program to be increased to twice the
space available on the PDP11/40.
2.13 Initial Conditions
When the system is first started after all the devices
on the Unibus have been reinitialised, the memory
management unit is disabled and the processor is
in kernel mode.
Under these circumstances, virtual (byte) ad-
dresses in the range 0 to 56K are mapped into iden-
tically valued physical addresses. However the high-
est page of the virtual address space is mapped into
the highest page of the physical address space, i.e.
on the PDP11/40 or 11/45, addresses in the range
0160000 to 0177777
are mapped into the range
0760000 to 0777777
2.14 Special Device Registers
The high page of physical memory is reserved for
various special registers associated with the proces-
sor and the peripheral devices. By sacrificing one
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