MSP430x2xx系列微控制器用户手册：英文版概览

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"MSP430x2xx 系列用户指南（英文版）" 本文档是Texas Instruments（TI）推出的MSP430x2xx系列微控制器的用户指南，详细介绍了该系列芯片的功能和操作。MSP430x2xx家族是低功耗、高性能的16位MCU，广泛应用于各种嵌入式系统设计中。这份英文版指南涵盖了从架构到各个模块的详细信息，帮助开发者全面理解并有效利用这些器件。 1. **架构**：MSP430x2xx系列采用了一种灵活的架构，设计时考虑了低功耗和高性能的需求。它包含一个CPU，以及多个可配置的外设模块，能够满足不同应用的需求。 2. **灵活的时钟系统**：该系列MCU具有灵活的时钟系统，能够根据应用需求调整工作频率，以实现低功耗运行或高速运算。 3. **嵌入式仿真**：内建的嵌入式仿真模块(EEM)支持在系统调试，使得开发过程更加便捷，无需额外的仿真硬件。 4. **地址空间**：包括闪存/ROM、RAM、外设模块、特殊功能寄存器(SFRs)和内存组织结构。这使得开发者可以有效地管理和访问不同的存储区域。 5. **系统复位和初始化**：系统复位包括布朗特复位(BOR)和其他类型，确保设备在复位后处于已知状态。设备在系统复位后的初始条件也进行了详细说明。 6. **中断**：MSP430x2xx支持非屏蔽中断(NMI)和屏蔽中断，中断处理机制和中断向量表为实时响应事件提供了基础。 7. **操作模式**：MCU可以进入多种低功耗模式，如空闲模式、掉电模式等，并且有明确的进入和退出策略。同时，文档还提供了低功耗应用的基本原则。 8. **CPU**：CPU部分包括了CPU介绍、CPU寄存器如程序计数器(PC)、堆栈指针(SP)、状态寄存器(SR)和常量生成器等，这些都是MCU执行指令和管理任务的核心组件。 9. **其他外设**：文档还详细介绍了数字I/O、定时器、串行接口（如UART、SPI、I2C模式）、比较器、模数转换器(ADC)、数模转换器(DAC)、以及其他的模拟和数字接口模块，这些外设为实现复杂系统功能提供了支持。通过这份用户指南，开发者可以获得MSP430x2xx系列微控制器的全面知识，从而能够高效地设计和优化基于该平台的嵌入式系统。

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18-7. MSP430 Baud Rate Generator......................................................................................... 481

18-8. BITCLK Baud Rate Timing ............................................................................................. 482

18-9. Receive Error ............................................................................................................. 485

18-10. Transmit Interrupt Operation ........................................................................................... 487

18-11. Receive Interrupt Operation ............................................................................................ 487

18-12. Glitch Suppression, USART Receive Not Started ................................................................... 489

18-13. Glitch Suppression, USART Activated ................................................................................ 489

19-1. USART Block Diagram: SPI Mode .................................................................................... 498

19-2. USART Master and External Slave.................................................................................... 500

19-3. USART Slave and External Master.................................................................................... 501

19-4. Master Transmit Enable State Diagram............................................................................... 501

19-5. Slave Transmit Enable State Diagram ................................................................................ 502

19-6. SPI Master Receive-Enable State Diagram .......................................................................... 502

19-7. SPI Slave Receive-Enable State Diagram............................................................................ 502

19-8. SPI Baud Rate Generator............................................................................................... 503

19-9. USART SPI Timing ...................................................................................................... 503

19-10. Transmit Interrupt Operation ........................................................................................... 504

19-11. Receive Interrupt Operation ............................................................................................ 505

19-12. Receive Interrupt State Diagram....................................................................................... 505

20-1. OA Block Diagram ....................................................................................................... 513

20-2. Two-Opamp Differential Amplifier...................................................................................... 516

20-3. Two-Opamp Differential Amplifier OAx Interconnections ........................................................... 517

20-4. Three-Opamp Differential Amplifier.................................................................................... 518

20-5. Three-Opamp Differential Amplifier OAx Interconnections ......................................................... 519

21-1. Comparator_A+ Block Diagram ........................................................................................ 524

21-2. Comparator_A+ Sample-And-Hold .................................................................................... 526

21-3. RC-Filter Response at the Output of the Comparator............................................................... 527

21-4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ...................................... 527

21-5. Comparator_A+ Interrupt System...................................................................................... 528

21-6. Temperature Measurement System................................................................................... 528

21-7. Timing for Temperature Measurement Systems..................................................................... 529

22-1. ADC10 Block Diagram .................................................................................................. 535

22-2. Analog Multiplexer ....................................................................................................... 536

22-3. Sample Timing ........................................................................................................... 538

22-4. Analog Input Equivalent Circuit ........................................................................................ 538

22-5. Single-Channel Single-Conversion Mode............................................................................. 540

22-6. Sequence-of-Channels Mode .......................................................................................... 541

22-7. Repeat-Single-Channel Mode .......................................................................................... 542

22-8. Repeat-Sequence-of-Channels Mode................................................................................. 543

22-9. One-Block Transfer ...................................................................................................... 545

22-10. State Diagram for Data Transfer Control in One-Block Transfer Mode........................................... 546

22-11. Two-Block Transfer ...................................................................................................... 547

22-12. State Diagram for Data Transfer Control in Two-Block Transfer Mode........................................... 548

22-13. Typical Temperature Sensor Transfer Function ..................................................................... 550

22-14. ADC10 Grounding and Noise Considerations (Internal V

REF

) ...................................................... 550

22-15. ADC10 Grounding and Noise Considerations (External V

REF

) ..................................................... 551

22-16. ADC10 Interrupt System ................................................................................................ 551

23-1. ADC12 Block Diagram .................................................................................................. 561

23-2. Analog Multiplexer ....................................................................................................... 562

List of Figures SLAU144J–December 2004–Revised July 2013

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23-3. Extended Sample Mode................................................................................................. 564

23-4. Pulse Sample Mode ..................................................................................................... 564

23-5. Analog Input Equivalent Circuit ........................................................................................ 565

23-6. Single-Channel, Single-Conversion Mode............................................................................ 566

23-7. Sequence-of-Channels Mode .......................................................................................... 567

23-8. Repeat-Single-Channel Mode .......................................................................................... 568

23-9. Repeat-Sequence-of-Channels Mode................................................................................. 569

23-10. Typical Temperature Sensor Transfer Function ..................................................................... 571

23-11. ADC12 Grounding and Noise Considerations........................................................................ 572

25-1. DAC12 Block Diagram .................................................................................................. 590

25-2. Output Voltage vs DAC12 Data, 12-Bit, Straight Binary Mode .................................................... 592

25-3. Output Voltage vs DAC12 Data, 12-Bit, 2s-Compliment Mode .................................................... 592

25-4. Negative Offset........................................................................................................... 593

25-5. Positive Offset ............................................................................................................ 593

25-6. DAC12 Group Update Example, Timer_A3 Trigger ................................................................. 594

26-1. SD16_A Block Diagram ................................................................................................. 600

26-2. Analog Input Equivalent Circuit ........................................................................................ 602

26-3. Comb Filter Frequency Response With OSR = 32 .................................................................. 603

26-4. Digital Filter Step Response and Conversion Points................................................................ 604

26-5. Used Bits of Digital Filter Output....................................................................................... 606

26-6. Input Voltage vs Digital Output......................................................................................... 607

26-7. Single Channel Operation .............................................................................................. 608

26-8. Typical Temperature Sensor Transfer Function ..................................................................... 609

27-1. Block Diagram of the SD24_A ......................................................................................... 618

27-2. Analog Input Equivalent Circuit ........................................................................................ 620

27-3. Comb Filter Frequency Response With OSR = 32 .................................................................. 622

27-4. Digital Filter Step Response and Conversion Points................................................................ 622

27-5. Used Bits of Digital Filter Output....................................................................................... 624

27-6. Input Voltage vs Digital Output......................................................................................... 625

27-7. Single Channel Operation - Example ................................................................................. 626

27-8. Grouped Channel Operation - Example .............................................................................. 627

27-9. Conversion Delay Using Preload - Example ......................................................................... 628

27-10. Start of Conversion Using Preload - Example ....................................................................... 628

27-11. Preload and Channel Synchronization ................................................................................ 629

27-12. Typical Temperature Sensor Transfer Function ..................................................................... 629

28-1. Large Implementation of the Embedded Emulation Module (EEM) ............................................... 640

SLAU144J–December 2004–Revised July 2013 List of Figures

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List of Tables

1-1. MSP430x2xx Family Enhancements.................................................................................... 27

2-1. Interrupt Sources, Flags, and Vectors .................................................................................. 37

2-2. Operating Modes For Basic Clock System............................................................................. 39

2-3. Connection of Unused Pins .............................................................................................. 41

3-1. Description of Status Register Bits...................................................................................... 46

3-2. Values of Constant Generators CG1, CG2 ............................................................................ 46

3-3. Source/Destination Operand Addressing Modes...................................................................... 48

3-4. Register Mode Description ............................................................................................... 49

3-5. Indexed Mode Description ............................................................................................... 50

3-6. Symbolic Mode Description .............................................................................................. 51

3-7. Absolute Mode Description............................................................................................... 52

3-8. Indirect Mode Description ................................................................................................ 53

3-9. Indirect Autoincrement Mode Description .............................................................................. 54

3-10. Immediate Mode Description............................................................................................. 55

3-11. Double Operand Instructions ............................................................................................ 57

3-12. Single Operand Instructions.............................................................................................. 58

3-13. Jump Instructions.......................................................................................................... 59

3-14. Interrupt and Reset Cycles............................................................................................... 60

3-15. Format-II Instruction Cycles and Lengths .............................................................................. 60

3-16. Format 1 Instruction Cycles and Lengths .............................................................................. 61

3-17. MSP430 Instruction Set .................................................................................................. 62

4-1. SR Bit Description ....................................................................................................... 121

4-2. Values of Constant Generators CG1, CG2........................................................................... 122

4-3. Source/Destination Addressing ........................................................................................ 125

4-4. MSP430 Double-Operand Instructions................................................................................ 143

4-5. MSP430 Single-Operand Instructions................................................................................. 143

4-6. Conditional Jump Instructions .......................................................................................... 144

4-7. Emulated Instructions ................................................................................................... 144

4-8. Interrupt, Return, and Reset Cycles and Length..................................................................... 145

4-9. MSP430 Format II Instruction Cycles and Length ................................................................... 145

4-10. MSP430 Format I Instructions Cycles and Length .................................................................. 146

4-11. Description of the Extension Word Bits for Register Mode......................................................... 147

4-12. Description of Extension Word Bits for Non-Register Modes ...................................................... 149

4-13. Extended Double-Operand Instructions............................................................................... 151

4-14. Extended Single-Operand Instructions................................................................................ 153

4-15. Extended Emulated Instructions ....................................................................................... 155

4-16. Address Instructions, Operate on 20-Bit Register Data............................................................. 156

4-17. MSP430X Format II Instruction Cycles and Length ................................................................. 157

4-18. MSP430X Format I Instruction Cycles and Length.................................................................. 158

4-19. Address Instruction Cycles and Length ............................................................................... 159

4-20. Instruction Map of MSP430X ........................................................................................... 160

5-1. Basic Clock Module+ Registers ........................................................................................ 282

6-1. DMA Transfer Modes.................................................................................................... 291

6-2. DMA Trigger Operation ................................................................................................. 297

6-3. Channel Priorities ........................................................................................................ 299

6-4. Maximum Single-Transfer DMA Cycle Time ......................................................................... 299

6-5. DMA Registers ........................................................................................................... 302

List of Tables SLAU144J–December 2004–Revised July 2013

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7-1. Erase Modes.............................................................................................................. 312

7-2. Write Modes .............................................................................................................. 315

7-3. Flash Access While BUSY = 1 ......................................................................................... 320

7-4. Flash Memory Registers ................................................................................................ 323

8-1. PxSEL and PxSEL2 ..................................................................................................... 329

8-2. Digital I/O Registers ..................................................................................................... 333

9-1. SVS Registers............................................................................................................ 339

10-1. Watchdog Timer+ Registers............................................................................................ 346

11-1. OP1 Addresses........................................................................................................... 351

11-2. RESHI Contents.......................................................................................................... 351

11-3. SUMEXT Contents....................................................................................................... 351

11-4. Hardware Multiplier Registers .......................................................................................... 354

12-1. Timer Modes.............................................................................................................. 358

12-2. Output Modes ............................................................................................................ 364

12-3. Timer_A3 Registers...................................................................................................... 369

13-1. Timer Modes.............................................................................................................. 377

13-2. TBCLx Load Events ..................................................................................................... 383

13-3. Compare Latch Operating Modes ..................................................................................... 383

13-4. Output Modes ............................................................................................................ 384

13-5. Timer_B Registers ....................................................................................................... 390

14-1. USI Registers............................................................................................................. 405

14-2. Word Access to USI Registers ......................................................................................... 405

15-1. Receive Error Conditions ............................................................................................... 418

15-2. BITCLK Modulation Pattern ............................................................................................ 420

15-3. BITCLK16 Modulation Pattern ......................................................................................... 421

15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................ 424

15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................ 425

15-6. USCI_A0 Control and Status Registers............................................................................... 428

15-7. USCI_A1 Control and Status Registers............................................................................... 428

16-1. UCxSTE Operation ...................................................................................................... 438

16-2. USCI_A0 and USCI_B0 Control and Status Registers ............................................................. 444

16-3. USCI_A1 and USCI_B1 Control and Status Registers ............................................................. 444

17-1. State Change Interrupt Flags........................................................................................... 465

17-2. USCI_B0 Control and Status Registers............................................................................... 467

17-3. USCI_B1 Control and Status Registers............................................................................... 467

18-1. Receive Error Conditions ............................................................................................... 480

18-2. Commonly Used Baud Rates, Baud Rate Data, and Errors ....................................................... 486

18-3. USART0 Control and Status Registers ............................................................................... 490

18-4. USART1 Control and Status Registers ............................................................................... 490

19-1. USART0 Control and Status Registers ............................................................................... 506

19-2. USART1 Control and Status Registers ............................................................................... 506

20-1. OA Output Configurations .............................................................................................. 514

20-2. OA Mode Select.......................................................................................................... 514

20-3. Two-Opamp Differential Amplifier Control Register Settings....................................................... 516

20-4. Two-Opamp Differential Amplifier Gain Settings..................................................................... 516

20-5. Three-Opamp Differential Amplifier Control Register Settings..................................................... 518

20-6. Three-Opamp Differential Amplifier Gain Settings................................................................... 518

20-7. OA Registers ............................................................................................................. 520

21-1. Comparator_A+ Registers .............................................................................................. 530

SLAU144J–December 2004–Revised July 2013 List of Tables

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22-1. Conversion Mode Summary............................................................................................ 539

22-2. Maximum DTC Cycle Time ............................................................................................. 549

22-3. ADC10 Registers......................................................................................................... 552

23-1. Conversion Mode Summary............................................................................................ 565

23-2. ADC12 Registers......................................................................................................... 574

24-1. Example SegmentA Structure.......................................................................................... 582

24-2. Supported Tags (Device Specific) ..................................................................................... 583

24-3. DCO Calibration Data (Device Specific) .............................................................................. 583

24-4. TAG_ADC12_1 Calibration Data (Device Specific) ................................................................. 584

25-1. DAC12 Full-Scale Range (V

REF

= V

eREF+

or V

REF+

) .................................................................... 591

25-2. DAC12 Registers......................................................................................................... 595

26-1. High Input Impedance Buffer ........................................................................................... 602

26-2. Sampling Capacitance .................................................................................................. 603

26-3. Data Format .............................................................................................................. 607

26-4. Conversion Mode Summary............................................................................................ 608

26-5. SD16_A Registers ....................................................................................................... 611

27-1. High Input Impedance Buffer ........................................................................................... 620

27-2. Sampling Capacitance .................................................................................................. 621

27-3. Data Format .............................................................................................................. 625

27-4. Conversion Mode Summary............................................................................................ 626

27-5. SD24_A Registers ....................................................................................................... 632

28-1. 2xx EEM Configurations ................................................................................................ 642

List of Tables SLAU144J–December 2004–Revised July 2013

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