IEEE 1801 UPF 2.0：低功耗集成电路设计与验证标准

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IEEE 1801 UPF2.0标准是一份由IEEE Computer Society的Design Automation Standards Committee和IEEE Standards Association Corporate Advisory Group联合发布的官方规范，专注于设计与验证低功耗集成电路。这份标准于2009年3月27日批准，目标是提供一套全面的方法和指南，帮助工程师在设计过程中优化电路的能效，以满足现代电子设备对低功耗的需求。该标准的主要内容涵盖了低功耗集成电路的设计原则、技术要求和验证方法。它强调了在芯片设计初期就要考虑功耗效率的重要性，提倡采用高效的电源管理策略和技术，如动态电压和频率调整（DVFS）、电源关断模式、以及有效的数字和模拟信号处理技术。通过遵循IEEE 1801 UPF2.0，设计者可以确保他们的产品能够在电池寿命有限的应用场景中实现最佳性能，同时保持良好的系统可靠性。对于半导体制造商如STMicroelectronics，他们获得了该标准的授权许可，允许他们在特定的时间（2009年5月27日）下载并使用这些资料，但需遵守IEEExplore上的相关限制。这份标准在2009年3月19日由IEEE-SA Standards Board批准，表明其在整个行业内具有权威性和有效性。版权方面，所有内容受IEEE Institute of Electrical and Electronics Engineers保护，2009年的版权归属IEEE。使用此标准时，必须遵守相应的版权规定，尊重知识产权。 IEEE 1801 UPF2.0是一个关键的工具，对于电子工程师、半导体设计师和系统架构师来说，它提供了指导，帮助他们在追求高性能的同时，降低能耗，实现绿色电子产品的目标。随着电子产品对能效的要求不断提高，理解和应用这一标准变得愈发重要。

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IEEE Standard for

Design and Verification of

Low Power Integrated Circuits

IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or

environmental protection in all circumstances. Implementers of the standard are responsible for

determining appropriate safety, security, environmental, and health practices or regulatory requirements.

This IEEE document is made available for use subject to important notices and legal disclaimers. These

notices and disclaimers appear in all publications containing this document and may be found under the

heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.”

They can also be obtained on request from IEEE or viewed at http://standards.ieee.org/IPR/

disclaimers.html.

1. Overview

1.1 Scope

This standard establishes a format used to define the low power design intent for electronic systems and

electronic intellectual property. The format provides the ability to specify the supply network, switches,

isolation, retention and other aspects relevant to power management of an electronic system. The standard

defines the relationship between the low power design specification and the logic design specification

captured via other formats (e.g., standard hardware description languages).

1.2 Purpose

The standard provides portability of low power design specifications that can be used with a variety of

commercial products throughout an electronic system design, analysis, verification and implementation

flow.

1.3 Key characteristics of the Unified Power Format (UPF)

The Unified Power Format (UPF) provides the ability for electronic systems to be designed with power as a

key consideration early in the process. UPF accomplishes this by allowing the specification of what was

traditionally physical implementation-based power information early in the design process—at the register

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VERIFICATION OF LOW POWER INTEGRATED CIRCUITS IEEE Std 1801-2009

— Place and Route tools read both the netlist and the UPF files and produce outputs, potentially

including an output UPF file.

UPF is a concise power design intent specification capability. Power design intent can be easily specified

over many elements in the design. A UPF specification can be included with the other deliverables of

intellectual property (IP) blocks and reused along with the other delivered IP. UPF supports various

methodologies through carefully defined semantics, flexibility in specification, and, when needed, defined

rational limitations that facilitate automation in verification and implementation.

A UPF specification defines how to create a supply network to supply power to each design element, how

the individual supply nets behave with respect to one another, and how the logic functionality is extended to

support dynamic power switching to these logic design elements. By controlling the operating voltages of

each supply net and whether the supply nets (and their connected design elements) are turned on or off, the

supply network only provides power at the level the functional areas of the chip need to complete the

computational task in a timely manner.

1.4 Power supply network design intent

Designing electronics to meet low power design constraints requires the specification of a power supply

network that can control the distribution of that supply to minimize energy consumption. UPF supports the

specification of the power supply distribution network so the supply network can be automatically

implemented at a relatively abstract level.

To help manage the complexity of the supply network specification, power domains are defined to group

elements from the logic hierarchy that share common supply needs. By default, all logic elements in a power

domain use the same primary supply. Additional supplies may be defined to serve different uses in a power

domain. In addition to the primary supply, UPF provides well-defined semantics for other supplies for both

verification and implementation contexts.

The supply network consists of supply ports, switches, and supply nets. Supply network objects are defined

within the logical hierarchy relative to the context of a power domain. Supply ports provide the supply

interface to the logical hierarchy and the power domain’s elements. Supply ports also provide the supply

interface to switches. Switches control the supply distribution. Supply nets connect supply ports.

Although there is an obvious inference to the actual wires and ports in the implemented hardware, a UPF

supply network is an abstraction of the electrical network on the chip. UPF defines no routing or layout

information. As the supply network is specified apart from the logic design, the logic design specification

remains independent of a specific power supply network specification.

Figure 2

shows an example supply distribution network for a hypothetical chip, mySoC. A top-level power

domain, mySoC_PD defined at the U_top instance level in the logical hierarchy, is defined with three

supply ports, Pbat, Pwall, and GND. These ports represent the off-chip power sources. A single switch

(S1) controls whether the chip receives its supply from Pbat or Pwall. Supply nets connect the output

from S1 to each power domain defined within the top-level power domain. mySoC_PD does not contain

any logic elements other than the root of the design U_top; its purpose is to define the interface to the off-

chip power sources and provide the top-level supply network.

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IEEE Std 1801-2009 IEEE STANDARD FOR DESIGN AND

Figure 2—A supply distribution network

Four power domains are defined at the next level, ana_PD, camera_PD, core_PD, and mp3_pd.

camera_PD, mp3_PD, and ana_PD each have a similar supply network internal to them. The primary

supply is switched (S4, S3, and S2), which indicates power to the logic elements in the domains can be

turned off. Unswitched isolation supplies are provided for camera_PD and mp3_PD.

core_PD contains a nested domain sub_PD. core_PD’s primary supply xRegSup is switched and

regulated within the domain, as it is the output of a regulator that has a switch (S5) driving the regulator’s

input (R1). Besides being the primary supply for core_PD, xRegSup also provides a retention supply for

sub_PD. The regulated supply is also connected to the output supply port (pRegSup) and, ultimately, the

switch input (S2) whose output drives the primary supply for ana_PD. This indicates ana_PD is powered

on only when core_PD is powered on. Within sub_PD, the primary supply is switched (S6), indicating

sub_PD can be powered down separately from core_PD, but holding the relationship that if core_PD is

powered down, so is sub_PD. sub_PD also contains two additional supplies (ret and BU). The ret

supply (which is used as a retention supply) has the same source as core_PD’s primary supply (the output

from switch S5) and the BU supply has the same source as the input to switch S5; therefore, the retention

supply (ret) is valid only when core_PD is on (switch S5 in the core_PD power domain). The BU

suppl

y is

provided for any retention elements whose state needs to be saved when both sub_PD and

core_PD are powered down.

This example demonstrates a methodology of locating the switches for a power domain’s supplies within the

power domain. UPF also supports placing the switches that can be switched off outside the power domain. If

this methodology were being used, switches S2, S3, and S4 would be located in mySoC_PD and additional

supply nets to connect the outputs of the switches to the corresponding ports of the nested power domains’

logical hierarchies would be created. Similarly, the switch S5 and regulator R1 would be placed in

mySoC_PD and the switch S6 moved up to core_PD. Either methodology is valid and the supply networks

are equivalent.

mySoC_PD

core_PD

xRegSup

sub_PD

ret

GND

SW_in

GN D

Pbat

Pwal l

mp3_PD

ISO

GN D

SW_i n

camera_PD

ISO

GN D

SW_i n

MP 3 _ PR I

u_PD_PRI

camera_PD_PRI

SW_in

ana_PD

GN D

SW_inana_PRI

GND

pRegSup

U_ana

U_mp3

U_core

U_camera

U_s ub

U_top

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IEEE 1801 UPF 2.0：低功耗集成电路设计与验证标准

IEEE Standard for Design and Verification of Low-Power Integrated Circuits

Unified Power Format(UPF)example

IEEE 1801-2015(3.0).pdf

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upf-guide.pdf

upf3.0 ieee1801 2015文档

ieee 1801-2015 upf 3.1

在集成电路设计中，如何应用IEEE Std 1801标准来有效管理功耗并提高设计效率？请结合《IEEE 1801标准：低功耗集成电路设计与验证》给出具体实例。

如何在集成电路设计中应用IEEE Std 1801标准进行功耗管理？请结合《IEEE 1801标准：低功耗集成电路设计与验证》给出具体实例。

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