MA35D1系列：工业级双核处理器，集成大容量DDR内存

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MA35D1 Series是一款由NuMicro制造的基于Arm Cortex-A35架构的双核工业处理器，其在2023年12月25日更新至版本1.07。这款处理器的主要特点是集成大容量的DDR内存，旨在提供高效能和灵活性，支持各种工业应用的需求。 1. **核心子系统** (Core Sub-system): MA35D1采用了Cortex-A35内核，这是一颗高性能的微处理器核心，具备低功耗、高效的处理能力，适合于对性能要求较高的实时控制任务。它可能包括多线程处理、超标量执行单元和先进的指令集架构，以优化程序执行速度和效率。 2. **内存子系统** (Memory Sub-system): 集成大容量DDR内存是MA35D1的一个关键特性，这意味着处理器可以直接访问高速存储器，有助于减少延迟，提高数据处理速度，适合处理大数据和图形密集型应用。同时，该内存支持多种规格，如DDR3或DDR4，以满足不同用户的需求。 3. **安全子系统** (Security Sub-system): 为了保障系统的安全性，MA35D1可能内置了安全控制功能，如硬件加密引擎、 TrustZone等，帮助保护数据和执行环境，防止未授权访问和攻击。 4. **显示与视频子系统** (Display and Video Sub-system): 作为一款工业级处理器，MA35D1可能具备高清视频解码和编码能力，支持HDMI输出，用于驱动外部显示器或者进行视频处理，适合需要图形处理和显示控制的应用。 5. **连接与I/O子系统** (Connectivity and I/O Sub-system): MA35D1很可能提供了丰富的I/O接口，如USB、UART、SPI、I2C等，以及可能的以太网接口，以便与其他设备通信和扩展功能。这对于物联网(IoT)、工业自动化和嵌入式系统设计至关重要。 2.1 **MA35D1系列特色** (2.1 MA35D1Series Features): 包括上述提到的各方面特性和优势，如高性能、低功耗、灵活性、高集成度、以及针对工业环境的耐用性设计。 3. **部件信息** (Parts Information): MA35D1 Series提供了不同的封装类型（3.1 Package Type），例如QFP或LQFP，便于根据实际应用选择合适的封装形式。此外，还可能有明确的命名规则（3.2 Naming Rule）帮助用户理解和识别不同版本或配置的处理器。 4. **选型指南** (3.3 MA35D1Series Selection Guide): 这部分会详细介绍如何根据项目需求（如性能、功耗、I/O需求等）来选择最适合的MA35D1型号，可能会包含性能参数比较表、功耗分析以及推荐应用场景示例。 MA35D1 Series是一款专为工业环境设计的高性能处理器，其集成的内存子系统和全面的I/O支持使其成为众多嵌入式和工业控制项目的理想选择。为了确保最佳性能和应用适配，开发者需要详细了解其规格、选型指南和相应的技术支持。

MA35D1 Series

Dec. 25, 2023 Page 16 of 285 Rev 1.07

MA35D1 SERIES DATASHEET

2 FEATURES

2.1 MA35D1 Series Features

Core Sub-system

Arm Cortex-A35

 Dual 64/32-bit Arm Cortex-A35 core running up to 800 MHz

 Built-in 32 Kbytes instruction and 32 Kbytes data L1 cache for each

core with Memory Management Unit (MMU)

 Built-in 512 Kbytes shared L2 cache with Snoop Control Unit (SCU)-

L2 cache protection

 Arm TrustZone

 Arm NEON SIMD Engine and FPU

 Arm Cryptographic Extension

 Armv8 debug logic

 Supports Generic Interrupt Controller (GIC) CPU interface

 Supports 64-bit count input for Generic Timer

Arm Cortex-M4

 32-bit Arm Cortex-M4 processor core running up to 180 MHz

 Built-in 16 Kbytes instruction and 16 Kbytes data cache

 Built-in Memory Protection Unit (MPU)

 Built-in Nested Vectored Interrupt Controller (NVIC)

 Hardware IEEE 754 compliant Floating-point Unit (FPU)

 DSP extension with hardware divider and single-cycle 32-bit

hardware multiplier

 24-bit system tick timer

 Programmble and maskable interrupt

 Low Power Sleep mode by WFI and WFE instructions

Arm CoreLink

GIC-400

Generic Interrupt

Controller (GIC)

 Up to 170 interrupts

– 16 Software Generated Interrupt (SGIs)

– 4 external Private Peripheral Interrupts (PPIs) for each

processor

– 1 internal PPI for each processor

– 130 Shared Peripheral Interrupt (SPIs)

 Interrupt Enabled or Disabled

 Interrupt Prioritized

 Interrupt to dual Arm Cortex-A35 processor core

 Level-sensitive interrupt

 Security Extensions

– Group 0 interrupt as Secure interrupts

– Group 1 interrupt as Non-secure interrupts

 Virtualization Extensions

Hardware Semaphore

 Eight hardware semaphores for inter-processor synchronization

MA35D1 Series

Dec. 25, 2023 Page 17 of 285 Rev 1.07

MA35D1 SERIES DATASHEET

 Support interrupt when semaphore released

Wormhole

 Supports two wormhole controllers for inter-processor

communication

 Supports interrupt for reset event and power state change event

 Four general event interrupts

 Eight 16-byte unidirectional message channels, four for each

processor

 Supports message recall mechanism

Watchdog

 Three Watchdogs, one for TrustZone Secure (TZS), one for

TrustZone Secure/Non-Secure (TZS/TZNS) and the other for SubM

 20-bit free running up counter for WDT time-out interval

 Supports multiple clock sources from LIRC (default selection),

PCLK/4096 or LXT with 9 selectable time-out period

 Able to wake up system from Power-down or Idle mode

 Time-out event to trigger interrupt or reset system

 Supports four WDT reset delay periods, including 1026, 130, 18 or 3

WDT_CLK reset delay period

 Configured to force WDT enabled on chip power-on or reset

Window Watchdog

 Three Window Watchdogs, one for TrustZone Secure (TZS), one for

TrustZone Secure/Non-Secure (TZS/TZNS) and the other for SubM

 Clock sourced from LIRC (default selection) or PCLK/4096; the

window set by 6-bit counter with 11-bit prescale

 Suspended in Idle/Power-down mode

Real-Time Clock (RTC)

 Real-Time Clock with a separate power domain (V

BAT

)

 RTC clock source including Low-speed external crystal oscillator

(LXT)

 RTC block including 64 bytes backup registers

 Able to wake up CPU

 Supports ±5ppm within 5 seconds software clock accuracy

compensation

 Supports Alarm registers (second, minute, hour, day, month, year)

 Supports RTC Time Tick and Alarm Match interrupt

 Automatic leap year recognition

 Supports 1 Hz clock to be Timer capture source for calibration

 Supports 1 pairs dynamic loop tamper pin or 2 individual tamper pin

External Clock Source

 24 MHz High-speed external crystal oscillator (HXT) for precise

timing operation

 32.7688 kHz Low-speed external crystal oscillator (LXT) for RTC

function and low-power operation

 Supports clock failure detection for external crystal oscillators and

exception generatation (NMI)

MA35D1 Series

Dec. 25, 2023 Page 18 of 285 Rev 1.07

MA35D1 SERIES DATASHEET

Internal Clock Source

 32 kHz Low-speed Internal RC oscillator (LIRC)

 12 MHz High-speed Internal RC oscillator (HIRC) trimmed to 5%

accuracy at -40 to 85°C

 Six on-chip PLLs up to 800 MHz on-chip PLL, sourced from HXT,

allows CPU operation up to the maximim CPU frequency

System Security Memory

Configuration Controller

(SSMCC)

 Three Arm CoreLink TZC-400 TrustZone Address Space Controllers

for seven AXI channels

 Configurable security attribution of SDRAM memory

 Security violation detection, report and interrupt generation

 Programmable SDRAM region for SubM system

 Write Protect of security configuration

System Security Peripheral

Configuration Controller

(SSPCC)

 Configurable security attribution of SRAM by boundary

 Configurable security attribution of GPIO by pin

 Configurable security attribution of peripherals

 Security violation detection, report and interrupt generation

 Write Protect of security configuration

 Debug interface protection mechanism

 Product Life-cycle Management

Temperature Sensor

 Built-in temperature sensor with ±5°C accuracy

Low Voltage Detect (LVD)

 Two-level LVD with low voltage detect interrupt (2.8V/2.6V)

Low Voltage Reset (LVR)

 LVR with 2.4V threshold voltage level.

Memory Sub-system

Boot Loader

 Factory pre-loaded 128 Kbytes mask ROM supporting four booting

modes

– Boot from USB (as device/host)

– Boot from SD/eMMC

– Boot from NAND Flash

– Boot from SPI Flash (SPI-NOR/SPI-NAND)

SRAM

 Up to 384 (128 + 256) KB on-chip SRAM

 Supports byte-, half-word- and word-access

 Supports PDMA operation

SDRAM

 Supports DDR2 (Double-Data-Rate 2), DDR3 (Double-Data-Rate 3)

and DDR3L (DDR3 Low Voltage) type of SDRAM

 Clock speed up to 533 MHz

 Supports 16-bit data width

 SDRAM burst length of 8

 Up to 2 memory ranks

 Maximum SDRAM size up to 2 GB (each chip select for 1 GB)

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