纳米级非易失性内存设计探索

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"这篇论文探讨了新兴纳米级非易失性内存的设计探索，旨在解决大数据时代下硬件平台的局限性，特别是针对数据密集型计算的需求。随着数据量的增长，现有的硬件平台面临内存墙、功耗墙以及先进CMOS技术节点的大漏电功率问题。文章提出需要设计一种能效高的硬件平台，支持未来大数据存储，并能处理图像和安全应用中的数据密集型处理。内存分为易失性和非易失性两种，非易失性内存如闪存和硬盘驱动器具有保持信息不需外部电源的特性，但速度较慢。新内存技术需要满足高密度集成、低能耗移动访问和高耐久性（能进行10^12次写入/擦除循环）等标准。作者Hao Yu和Yuhao Wang来自新加坡南洋理工大学电子与电气工程学院，他们在论文中深入讨论了这些关键点。" 在当前的计算环境中，大数据分析已成为国家层面的重要需求，特别是在网络安全领域，需要快速处理海量数据以检测恶意攻击。传统的内存技术，如SRAM和DRAM，虽然访问速度快，但数据在断电后会丢失。而非易失性内存，如闪存和HDD，虽然可以保持数据，但速度较慢，无法满足大数据应用的需求。因此，研究新型非易失性内存，尤其是纳米级别的，成为解决这一问题的关键。新型非易失性内存技术需要满足三个主要标准：首先，可扩展性以实现高密度集成，这意味着单位面积内可以存储更多的信息；其次，低能量消耗对于移动设备尤其重要，因为这直接影响到设备的电池寿命和便携性；最后，高耐久性是衡量其寿命的重要指标，能够承受大量写入和擦除操作而不会损坏。这样的内存技术将极大地提升计算机的启动速度、数据传输效率，改变我们的生活和工作方式。论文作者的研究工作集中在如何设计这种新型内存，以适应未来的数据存储和处理需求。他们探索了纳米级工艺在提高内存性能和能效方面的作用，同时考虑了技术的可行性、成本效益和实际应用潜力。通过这样的设计探索，期望能找到一种既具备高速访问能力，又能保持数据的非易失性存储解决方案，为大数据时代的信息处理提供革命性的技术支持。这项研究对理解并推动非易失性内存技术的发展具有重要意义，它将直接影响到大数据时代的硬件架构设计，提高数据处理效率，降低能源消耗，并可能开启新的计算范式。

1.2 Traditional Semiconductor Memories 5

Fig. 1.5 Typical memory hierarchy of a computer system (latency measured in processor cycles)

According to volatility, the semiconductor memories can be further classiﬁed

into volatile memory and nonvolatile memory. Volatile memory stores data as

electrical signals and loses its data when the chip is powered off. Currently, the most

commonly used volatile memories are SRAM and DRAM, whose data is indicated

by the electrical voltage levels. On the contrary, nonvolatile memory is able to

retain its data even when the chip is turned off, as its data is mostly preserved by

nonelectrical states. For instance, bits in programmable read-only memory (PROM)

are denoted by whether the fuses of individual memory cells are burned. In this

part, the principles and operations of volatile SRAM/DRAM and nonvolatile ﬂash

memory will be brieﬂy introduced (Fig. 1.5).

1.2.1.1 Static Random-Access Memory

A typical CMOS SRAM cell consists of six transistors, as shown in Fig. 1.6.

The ﬂip-ﬂop formed by M1–M4 holds the stored bit. The term static is derived

from the fact that the cell does not need to be refreshed like dynamic RAM and the

data can be retained as long as the power is supplied. M5and M6, connected with

the word-line and two bit-lines, are used as access transistors to select target cells.

There are three operation states for a SRAM cell: write, read, and standby. To a

write operation, the value to be written needs to be applied on both bit-lines, namely,

BL and

BL, in a complementary manner. Assume we wish to write “0” to the cell,

i.e., Q to be “0” and

Q to be “1”; the BL is driven low and BL high. Once M5and

M6are turned on by setting WL “1,” the bit-line drivers will override the previous

6 1 Introduction

Fig. 1.6 A 6T SRAM cell structure with leakage paths in standby state. The bit-lines are

precharged high and assume the stored data is “1” at Q

stored value. In order to easily override the previous state in the self-reinforced ﬂip-

ﬂop, the bit-line drivers are required to be designed stronger than the transistors in

ﬂip-ﬂop.

For a read operation, both bit-lines are prechargedhigh before the start of the read

cycle, and the turning on of the word-line signiﬁes the start of the read operation.

Because of the opposite voltages at Q and

Q, one of the bit-lines will be pulled

down by the cell, and the discharging of one of the bit-lines is then detected by the

bit-line sense ampliﬁer. In voltage mode sensing scheme, the sign of bit-line voltage

difference V (V

minus V

) determines the value of stored bit. A V in tens

of millivolts is signiﬁcant enough to efﬁciently distinguish which bit-line is being

discharged. For example, assume the stored bit is “1” at Q and “0” at

Q, and once

the WL is asserted, the

BL will discharge towards “0”; when a positive V of tens

of millivolts is gained, the latch-based sense ampliﬁer will amplify the small voltage

difference with positive feedback and ﬁnally output logic “1” as result.

When the word-line (WL) is connected to ground, turning off the two access

transistors, the cell is in the standby state. During the standby state, the two cross-

coupled inverters will reinforce each other due to the positive feedback, the value

is preserved as long as the power is supplied. One prominent problem regarding

SRAM in standby state is severe subthreshold leakage. Subthreshold leakage is

the drain–source current of a transistor when the gate–source voltage is less than

the threshold voltage. The subthreshold current depends exponentially on threshold

voltage, which results in large subthreshold current in deep-submicron regime.

Figure 1.6 shows three leakage paths in one SRAM cell, assuming the stored bit

is “1” at Q. Note that the BL and

BL are always precharged to V

to facilitate

future read operation. Regardless of the stored value, there always will be three

transistors consuming leakage power.

1.2 Traditional Semiconductor Memories 7

cell

Fig. 1.7 The circuit diagram

of 1T1C DRAM cell structure

Compared to other memory technologies, SRAM is able to provide fastest access

speed, but the advantage comes as a tradeoff against density and power. As one

SRAM cell requires silicon area for six transistors, SRAM has very limited density

and hence is more expensive than other memory technologies. In addition, it is very

power consuming due to the leakage problem at standby state. Therefore, SRAM

serves best in applications where high performance is the main concern and the

capacity is not signiﬁcant, namely the caches for processors.

1.2.1.2 Dynamic Random-Access Memory

The philosophy behind DRAM is simplicity. Unlike SRAM where one cell is

composed of six transistors, each individual DRAM cell consists of only one

capacitor and one access transistor. The data “0” or “1’ is represented by whether

the capacitor is fully charged or discharged. However, the electrical charge on the

capacitor will gradually leak away, and after a period of time, the voltage on the

capacitor is so low for the sense ampliﬁer to differentiate between “1” and “0.”

Therefore, unlike SRAM in which the data can be retained as long as the power is

supplied, the retention time for DRAM is ﬁnite and all DRAM cells need to be read

out and written back periodically to ensure data integrity. Typically, the cells are

refreshed once every 32 ms or 64 ms. This process is known as refresh, and this is

how the name of dynamic RAM is derived. Figure 1.7 shows the circuit diagram of

such 1T1C structure DRAM cell.

To write a DRAM cell, the bit-line is ﬁrst set high or low based on the

value to write. After the access transistor is turned on by the asserting word-

line, the capacitor in the selected cell is charged to “1” or discharged to “0.”

Because the access takes place through an NMOS transistor, there exists a V

drop

during the write “1.” In order to prevent this V

drop and maintain a long refresh

period, the word-line driving voltage is usually boosted to V

D V

C V

To read a DRAM cell, the bit-line is precharged to V

=2 andthentheword-

line is enabled. Due to the charge sharing, the bit-line voltage will slightly decrease

or increase depending on the voltage that the capacitor was previously charged to,

i.e., V

or 0. If it is previously charged, the charge sharing will slightly boost

the bit-line voltage; otherwise, some charge will be distributed from bit-line to cell

8 1 Introduction

n+n+

p-substrate

floating gate

control gate

oxide

Fig. 1.8 The cross section of

a ﬂoating gate transistor

capacitor. In both cases, the voltage of the storage capacitor will be changed after

the read operation; thus the read operation is called destructive, and an instant write

back is required. A slight voltage change on the bit-line can be calculated by

V D˙

cell

C C

bitline

: (1.1)

The sign of V depends on the state of the storage capacitor. In modern DRAM

devices, the capacitance of a storage capacitor is far smaller than the capacitance

of the bit-line. Typically, the capacitance of a storage capacitor is one-tenth of

the capacitance of the long bit-line that is connected to hundreds or thousands of

other cells. The relative capacitance values create the scenario that when the small

charge contained in a storage capacitor is placed on the bit-line, the resulting voltage

on the bit-line is small and difﬁcult to measure in an absolute sense. In DRAM

devices, the voltage sensing problem is resolved through the use of a differential

sense ampliﬁer that compares the voltage of the bit-line to a reference voltage.

The use of differential sense ampliﬁer, in turn, introduces some requirements on

the DRAM array structure. Particularly, instead of a single bit-line, a pair of bit-lines

needs to be used to sense the voltage value contained in any DRAM cell. In addition,

in order to ensure that the voltage and capacitance values on the pair of bit-lines are

closely matched, the bit-lines must be closely matched in terms of path lengths and

the number of cells attached. The above requirements lead to two distinctly different

array structures: open bit-line structures and folded bit-line structures.

1.2.1.3 Flash Nonvolatile Memory

Flash memory is the most widely used nonvolatile memory technology today.

The key device in this prevailing memory is ﬂoating gate transistors. A ﬁgure of

cross section of a ﬂoating gate transistor is shown in Fig. 1.8. Unlike a MOSFET

transistor, an additional ﬂoating gate is added between the control gate and channel.

Isolated by oxide layers, ﬂoating gate is able to trap charges and keep them for years.

Therefore, the FG-transistor encodes data based on whether electrons are trapped

and is able to retain data without power. That is where “nonvolatile” is derived from.

1.2 Traditional Semiconductor Memories 9

bit-line

NAND flash memory

NOR flash memory

INT

OFF

INT

Fig. 1.9 Two common layouts for ﬂash memory: NOR ﬂash memory and NAND ﬂash memory

The principle of read operation can be described as follows. When no charges

are trapped in ﬂoating gate, the FG-transistor has a threshold voltage of V

th0

;when

negative charges are trapped, they attract positive charges of control gate, thus higher

control gate voltage is required to turn on the channel,which produces a higher

threshold voltage V

th1

. By applying intermediate control gate voltage V

th0

and V

th1

and measuring current, the state of device can be known.

The write operation of FG-transistor involves injecting or pulling electrons across

the oxide barrier. There are two ways to achieve this, quantum tunneling and hot

electron injection. In quantum tunneling scenario, high voltage is applied on control

gate, quantum tunneling will take place between the ﬂoating gate and channel, and

electrons can travel across the oxide barrier. For hot electron injection scenario,

electrons are accelerated under high electrical ﬁeld in the channel till its energy is

high enough to penetrate the oxide layer. Note that electrons with high energy will

damage the oxide lattice, and such damage will accumulate and lead to a limited

write cycles, which is typically around 10

cycles.

There are two common layouts for ﬂash memory, as shown in Fig. 1.9,

NAND ﬂash memory with FG-transistors in series and NOR ﬂash memory with

FG-transistors in parallel. The names NAND and NOR are derived from the fact

that their connection fashion in series or parallel resembles a NAND gate or NOR

gate. NAND layout has the density advantage over NOR layout because each row

only has one ground connection and thus is widely used for external storage. NOR

layout has lower latency and thus is widely used in embedded systems, where

high performance is required. Figure 1.9 also shows how the read of NAND and

NOR ﬂash memory can be achieved. The relationship between the different applied

voltage magnitudes is shown as follows:

OFF

th0

INT

th1

jV

HIGH

j: (1.2)

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