RDA Microelectronics, Inc. RDA5807NP FM Tuner V1.2
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3.5 Control Interface
The RDA5807FP only supports I
2
The I
C control
interface.
2
C interface is compliant to I
2
C Bus
Specification 2.1. It includes two pins: SCLK and
SDIO. A I
2
C interface transfer begins with START
condition, a command byte and data bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (0010000b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes
is read out from RDA5807FP. There is no visible
register address in I
2
C interface transfers. The I
2
3.6 I
C
interface has a fixed start register address (0x02h
for write transfer and 0x0Ah for read transfer), and
an internal incremental address counter. If register
address meets the end of register file, 0x3Ah,
register address will wrap back to 0x00h. For write
transfer, MCU programs registers from register
0x02h high byte, then register 0x02h low byte,
then register 0x03h high byte, till the last register.
RDA5807FP always gives out ACK after every
byte, and MCU gives out STOP condition when
register programming is finished. For read transfer,
after command byte from MCU, RDA5807FP
sends out register 0x0Ah high byte, then register
0x0Ah low byte, then register 0x0Bh high byte, till
receives NACK from MCU. MCU gives out ACK
for data bytes besides last data byte. MCU gives
out NACK for last data byte, and then
RDA5807FP will return the bus to MCU, and MCU
will give out STOP condition.
2
The RDA5807FP supports I
S Audio Data Interface
2
S (Inter_IC Sound
Bus) audio interface. The interface is fully
compliant with I
2
S bus specification. When setting
I2SEN bit high, RDA5807FP will output SCK, WS,
SD signals from GPIO3, GPIO1, GPIO2 as I
2
S
master and transmitter, the sample rate is
48Kbps,44.1kbps,32kbps….. RDA5807FP also
support as I
2
3.7 GPIO Outputs
S slaver mode and transmitter, the
sample rate is less than 100kbps.
The RDA5807FP has three GPIOs. The function
of GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is set to low, GPIO pins could be
programmed to output low or high or high-Z, or be
programmed to output interrupt and stereo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 could be programmed to
output a low interrupt (interrupt will be generated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VDD supplies
or the ENABLE bit.
SCK
MSB
SD
WS
1 SCK
LEFT CHANNEL
LSB MSB
1 SCK
RIGHT CHANNEL
LSB
Figure 3-2 I2S Digital Audio Format