NXP4330应用处理器规格书V1.07：Cortex-A9四核1.4GHz，支持LPDDR2/3/LVDDR3/DDR3

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NXP4330是一款由韩国Nexell Co., Ltd.开发的高性能应用处理器，它是S5P4418的前身。这款芯片采用Cortex-A9四核架构，主频高达1.4GHz，支持低功耗内存选项，包括LPDDR2、LPDDR3、LVDDR3（低电压DDR3）以及DDR3 SDRAM，最高可支持2GB的存储容量。其设计旨在提供高效能和灵活性，适用于多种嵌入式和工业级应用。该规格书V1.07包含了多个版本的更新历史，确保了技术的最新性和可靠性。以下是主要更改点： 1. **V0.81**：首次发布，文档基础版本。 2. **V0.82**：增加了VDDBallListTable和GNDBallListTable，有助于理解引脚布局和电路连接。 3. **V0.83**：重新编号所有图形和表格，提高文档结构的清晰度。 4. **V0.91**：添加了电气特性部分，提供了关于电压、电流等关键参数的详细说明；同时修改了系统控制部分的MDIV值，并加入了AC97控制器的块图。 5. **V0.92**：调整了UART Ch0和Ch1的基地址，优化了串口通信接口；在GPIO控制器部分增加了GPIOx EVENT DETECT MODE EXTENDED REGISTER（GPIOxDETMODEEX）。 6. **V0.93**：增加了IPReset信息于系统控制部分，强化了复位功能。 7. **V0.94**：增添了系统控制中的Tie Off信息和Register描述，以及AXI总线信息。此外，VIP0和VIP1的基地址也进行了更新；内部上拉/下拉电阻信息被包含进来，增强了信号完整性处理。 NXP4330的这些改动表明了其对细节的关注和对用户使用的考虑，使得工程师们能够更好地理解和利用这款处理器的各种特性。对于那些在嵌入式系统设计中寻求高性能和多功能性的设计师来说，这个规格书是不可或缺的参考资料。通过深入研究这份文档，设计师可以了解如何配置系统，优化内存管理，以及充分利用GPIO、UART和视频输入处理器等功能，从而打造出高效能且稳定的系统。

Section 1. Product Overview

Section 27. I2S ........................................................................................................................... 587

27.1 Overview ........................................................................................................................................................................................ 588

27.1.1 FEATURES ............................................................................................................................................................................. 588

27.2 Functional Description ............................................................................................................................................................ 589

27.2.1 BASIC CLOCK TREE ............................................................................................................................................................. 590

27.2.2 I2S-BUS FORMAT ................................................................................................................................................................ 590

27.2.3 SAMPLING FREQUENCY AND MASTER CLOCK.................................................................................................................. 592

27.2.4 I2S CLOCK MAPPING TABLE .............................................................................................................................................. 592

27.3 Programming Guide ................................................................................................................................................................. 593

27.3.1 TX CHANNEL ....................................................................................................................................................................... 593

27.3.2 RX CHANNEL ....................................................................................................................................................................... 595

27.3.3 I2S-CONTROLLER INITIALIZE............................................................................................................................................. 597

27.3.4 NOTES .................................................................................................................................................................................. 597

27.4 Register Summary ..................................................................................................................................................................... 599

Section 28. AC97 ....................................................................................................................... 602

28.1 Overview ........................................................................................................................................................................................ 603

28.1.1 FEATURES ............................................................................................................................................................................. 603

28.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 603

28.2 Functional Description ............................................................................................................................................................ 604

28.2.1 INTERNAL DATA PATH ....................................................................................................................................................... 604

28.2.2 OPERATION FLOW CHART................................................................................................................................................. 604

28.2.3 AC-LINK DIGITAL INTERFACE PROTOCOL ....................................................................................................................... 605

28.2.3.1 AC-link Output Frame (SDATA_OUT) ................................................................................................. 606

28.2.3.2 AC-link Input Frame (SDATA_IN) .......................................................................................................... 607

28.2.4 AC97 POWER-DOWN ....................................................................................................................................................... 609

28.2.4.1 Powering Down the AC-Link .................................................................................................................. 609

28.2.4.2 Waking Up the AC-Link - Wake Up Triggered by the AC97 Controller ........................... 609

28.2.4.3 Cold AC97 Reset ........................................................................................................................................... 610

28.2.4.4 Warm AC97 Reset ........................................................................................................................................ 610

28.2.4.5 AC97 State Diagram.................................................................................................................................... 611

28.3 Register Summary ..................................................................................................................................................................... 612

Section 29. SPDIF TX ................................................................................................................ 616

29.1 Overview ........................................................................................................................................................................................ 617

29.1.1 FEATURES ............................................................................................................................................................................. 617

29.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 617

29.2 Functional Description ............................................................................................................................................................ 619

29.2.1 DATA FORMAT OF SPDIF................................................................................................................................................. 619

29.2.1.1 Frame Format ................................................................................................................................................. 619

29.2.1.2 Sub-frame Format (IEC 60958) .............................................................................................................. 620

Section 1. Product Overview

29.2.2 CHANNEL CODING ............................................................................................................................................................. 620

29.2.3 PREAMBLE ............................................................................................................................................................................ 621

29.2.4 NON-LINEAR PCM ENCODED SOURCE (IEC 61937) ................................................................................................ 621

29.2.5 SPDIF OPERATION ............................................................................................................................................................ 622

29.2.6 SHADOWED REGISTER ........................................................................................................................................................ 623

29.3 Register Summary ..................................................................................................................................................................... 624

Section 30. SPDIF RX ................................................................................................................ 629

30.1 Overview ........................................................................................................................................................................................ 630

30.1.1 FEATURES ............................................................................................................................................................................. 630

30.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 630

30.2 Functional Description ............................................................................................................................................................ 631

30.3 Register Summary ..................................................................................................................................................................... 632

Section 31. PDM ........................................................................................................................ 636

31.1 Overview ........................................................................................................................................................................................ 637

31.1.1 FEATURES ............................................................................................................................................................................. 637

31.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 637

31.1.3 PDM APPLICATION NOTE ................................................................................................................................................ 637

31.1.3.1 Butterworth Filter Configuration ........................................................................................................... 637

31.2 Register Summary ..................................................................................................................................................................... 639

Section 32. Display Architecture ............................................................................................ 641

32.1 Overview ........................................................................................................................................................................................ 642

32.1.1 FEATURES ............................................................................................................................................................................. 642

32.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 642

32.2 TFT/MPU Interface .................................................................................................................................................................... 643

32.3 Register Summary ..................................................................................................................................................................... 644

Section 33. Multi Layer Controller (MLC) ............................................................................ 646

33.1 Overview ........................................................................................................................................................................................ 647

33.1.1 FEATURES ............................................................................................................................................................................. 647

33.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 648

33.2 Dual Register Set Architecture ............................................................................................................................................ 649

33.3 MLC Global parameters .......................................................................................................................................................... 650

33.3.1 SCREEN SIZE......................................................................................................................................................................... 650

33.3.2 PRIORITY .............................................................................................................................................................................. 650

33.3.3 FIELD MODE ........................................................................................................................................................................ 651

33.3.4 BACKGROUND COLOR ........................................................................................................................................................ 651

33.4 Per-layer parameters ................................................................................................................................................................ 652

33.4.1 ENABLE ................................................................................................................................................................................. 653

Section 1. Product Overview

33.4.2 LOCK CONTROL ................................................................................................................................................................... 653

33.4.3 POSITION ............................................................................................................................................................................. 653

33.4.4 PIXEL FORMAT ..................................................................................................................................................................... 654

33.4.4.1 RGB layer format .......................................................................................................................................... 654

33.4.4.2 Video layer format ....................................................................................................................................... 655

33.4.4.3 Layer blending ............................................................................................................................................... 656

33.4.5 ADDRESS GENERATION ...................................................................................................................................................... 658

33.4.5.1 RGB layer address generation ................................................................................................................ 658

33.4.5.2 Video layer address generation ............................................................................................................ 658

33.4.6 VIDEO LAYER SPECIFIC PARAMETERS ................................................................................................................................ 659

33.4.7 SCALE FUNCTION ................................................................................................................................................................ 659

33.4.8 COLOR CONTROL ................................................................................................................................................................ 660

33.4.8.1 Luminance Enhancement .......................................................................................................................... 660

33.4.8.2 Chrominance Enhancement .................................................................................................................... 661

33.4.9 GAMMA CORRECTION ....................................................................................................................................................... 663

33.5 Clock Generation ....................................................................................................................................................................... 665

33.6 Register Sumarry ........................................................................................................................................................................ 666

Section 34. Display Controller (DPC) .................................................................................... 677

34.1 Overview ........................................................................................................................................................................................ 678

34.1.1 FEATURES ............................................................................................................................................................................. 678

34.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 678

34.2 Sync Generator ........................................................................................................................................................................... 679

34.2.1 CLOCK GENERATION ........................................................................................................................................................... 680

34.2.2 FORMAT ............................................................................................................................................................................... 682

34.2.3 SYNC SIGNALS ..................................................................................................................................................................... 684

34.2.4 SCAN MODE ........................................................................................................................................................................ 689

34.2.5 DELAY ................................................................................................................................................................................... 689

34.2.6 INTERRUPT ........................................................................................................................................................................... 689

34.2.7 MPU (I80) TYPE SYNC SIGNALS ..................................................................................................................................... 690

34.2.8 ODD/EVEN FIELD FLAG ..................................................................................................................................................... 691

34.3 Register Summary ..................................................................................................................................................................... 692

Section 35. Scaler ...................................................................................................................... 702

35.1 Overview ........................................................................................................................................................................................ 703

35.1.1 FEATURES ............................................................................................................................................................................. 703

35.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 703

35.2 Functional Description ............................................................................................................................................................ 704

35.2.1 DIGITAL FILTER CHARACTERISTICS ...................................................................................................................... 704

35.2.1.1 Horizontal Filter (5-Tab FIR Filter) Frequency Response and Group Delay..................... 704

35.2.1.2 Vertical Filter (3-Tab FIR Filter) Frequency Response and Group Delay ........................... 704

35.3 Programming Guide ................................................................................................................................................................. 706

Section 1. Product Overview

35.3.1 CONFIGURATION ................................................................................................................................................................. 706

35.3.2 RUN ..................................................................................................................................................................................... 706

35.4 Register Summary ..................................................................................................................................................................... 708

Section 36. LVDS ....................................................................................................................... 715

36.1 Overview ........................................................................................................................................................................................ 716

36.1.1 FEATURES ............................................................................................................................................................................. 716

36.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 716

36.2 Functional Description ............................................................................................................................................................ 717

36.2.1 LVDS DATA PACKING FORMAT ........................................................................................................................................ 717

36.2.2 LVDS APPLICATION NOTE ............................................................................................................................................... 718

36.2.3 SKEW CONTROL BETWEEN OUTPUT DATA AND CLOCK .................................................................................................. 718

36.2.4 ELECTRICAL CHARACTERISTICS ........................................................................................................................................... 719

36.3 Register Summary ..................................................................................................................................................................... 720

36.4 DisplayTop Register Summary ............................................................................................................................................ 726

Section 37. HDMI ...................................................................................................................... 727

37.1 Overview ........................................................................................................................................................................................ 728

37.1.1 FEATURES ............................................................................................................................................................................. 728

37.1.2 BLOCK DIAGRAM ................................................................................................................................................................ 729

37.2 Functional Description ............................................................................................................................................................ 730

37.2.1 SELECT RGB VIDEO DATA FOR HDMI ........................................................................................................................... 730

37.2.2 HDMI CONVERTER ............................................................................................................................................................ 730

37.2.3 HDMI LINK ....................................................................................................................................................................... 731

37.2.3.1 Video Input Interface .................................................................................................................................. 731

37.2.3.2 Audio Input Interface ................................................................................................................................. 737

37.2.3.3 HPD ..................................................................................................................................................................... 737

37.2.3.4 CEC ...................................................................................................................................................................... 738

37.2.3.5 Interrupt Timing ............................................................................................................................................ 738

37.2.3.6 HDCP KEY Management ........................................................................................................................... 738

37.3 Register Summary ..................................................................................................................................................................... 740

37.3.1 CONTROL REGISTERS ......................................................................................................................................................... 740

37.3.2 CORE REGISTERS ................................................................................................................................................................. 744

37.3.3 AES REGISTERS ................................................................................................................................................................... 784

37.3.4 SPDIF REGISTERS ............................................................................................................................................................... 785

37.3.5 I2S REGISTERS .................................................................................................................................................................... 797

37.3.6 CEC REGISTERS .................................................................................................................................................................. 812

37.4 HDMI PHY ..................................................................................................................................................................................... 822

37.4.1 PHY CONFIGURATION CHANGE THROUGH APB ......................................................................................................... 822

37.4.2 PHY READY SEQUENCE ............................................................................................................................................. 822

37.4.3 HDMI PHY CONFIGURATION .......................................................................................................................................... 823

37.4.4 HDMI PHY REGISTER SUMMARY ................................................................................................................................... 824

Section 1. Product Overview

37.5 HDMI Application Sequences .............................................................................................................................................. 826

37.6 DisplayTop Register Summary ............................................................................................................................................ 827

Section 38. MIPI ........................................................................................................................ 828

38.1 Overview ........................................................................................................................................................................................ 829

38.1.1 FEATURES ............................................................................................................................................................................. 829

38.2 DSIM 831

38.2.1 BLOCK DIAGRAM OF MIPI DSI SYSTEM ........................................................................................................................ 831

38.2.2 INTERFACES AND PROTOCOL ............................................................................................................................................ 833

38.2.3 CONFIGURATION ................................................................................................................................................................. 838

38.2.4 PLL ....................................................................................................................................................................................... 838

38.2.5 BUFFER ................................................................................................................................................................................. 838

38.2.6 DSIM REGISTER SUMMARY .............................................................................................................................................. 838

38.3 CSIS 855

38.3.1 INTERFACES AND PROTOCOL ............................................................................................................................................ 855

38.3.1.1 D-PHY layer FSM .......................................................................................................................................... 855

38.3.1.2 PPI interface timing & protocol ............................................................................................................ 855

38.3.2 CONFIGURATION ................................................................................................................................................................. 858

38.3.3 INTERRUPT ........................................................................................................................................................................... 858

38.3.4 CLOCK SPECIFICATION ........................................................................................................................................................ 858

38.3.5 CSIS REGISTER SUMMARY ................................................................................................................................................ 859

38.4 D-PHY .............................................................................................................................................................................................. 867

38.4.1 ARCHITECTURE .................................................................................................................................................................... 867

38.4.1.1 PLL and Clock Lane Connection ........................................................................................................... 867

38.4.1.2 Data Lane Connection................................................................................................................................ 867

38.4.1.3 IP Structure ...................................................................................................................................................... 868

38.4.1.4 Power Consumption .................................................................................................................................... 868

38.4.1.5 PAD Signals ..................................................................................................................................................... 869

38.4.1.6 Package and Board Connection Guideline ...................................................................................... 870

38.4.1.7 Core Interface Timing Diagram ............................................................................................................. 870

Section 39. Video Input Processor (VIP) .............................................................................. 875

39.1 Overview ........................................................................................................................................................................................ 876

39.1.1 FEATURES ............................................................................................................................................................................. 876

39.2 VIP Interconnection .................................................................................................................................................................. 877

39.2.1 BLOCK DIAGRAM ................................................................................................................................................................ 877

39.2.2 CLOCK GENERATION .......................................................................................................................................................... 877

39.3 Video Input Port ........................................................................................................................................................................ 878

39.3.1 BLOCK DIAGRAM ................................................................................................................................................................ 878

39.3.2 SYNC GENERATION ............................................................................................................................................................ 878

39.3.3 EXTERNAL DATA VALID AND FIELD ................................................................................................................................. 882

39.3.4 DATA ORDER ...................................................................................................................................................................... 883

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