UM11126 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
User manual Rev. 1.3 — 10 May 2019 17 of 1148
NXP Semiconductors
UM11126
Chapter 3: LPC55S6x Nested Vectored Interrupt Controller (NVIC)
4 GPIO_INT0_IRQ0 Pin interrupt 0 or pattern match engine slice 0. PSTAT - pin interrupt status.
5 GPIO_INT0_IRQ1 Pin interrupt 1or pattern match engine slice 1. PSTAT - pin interrupt status.
6 GPIO_INT0_IRQ2 Pin interrupt 2 or pattern match engine slice 2. PSTAT - pin interrupt status.
7 GPIO_INT0_IRQ3 Pin interrupt 3 or pattern match engine slice 3. PSTAT - pin interrupt status.
8 UTICK Micro-tick timer. INTR.
9 MRT Multi-rate timer. Global MRT interrupts: GFLAG0,
1, 2, 3.
10 CTIMER0 Standard counter/timer CTIMER0. Match and capture interrupts.
11 CTIMER1 Standard counter/timer CTIMER1. Match and capture interrupts.
12 SCT SCTimer. EVFLAG SCT event.
13 CTIMER3 Standard counter/timer CTIMER3. Match and capture interrupts.
14 Flexcomm Interface 0 Flexcomm Interface 0 (USART, SPI, I
2
C, I
2
S). See enable read and set register
of this module
15 Flexcomm Interface 1 Flexcomm Interface 1 (USART, SPI, I
2
C, I
2
S).
Same as Flexcomm0.
16 Flexcomm Interface 2 Flexcomm Interface 2 (USART, SPI, I
2
C, I
2
S) Same as Flexcomm0
17 Flexcomm Interface 3 Flexcomm Interface 3 (USART, SPI, I
2
C, I
2
S) Same as Flexcomm0.
18 Flexcomm Interface 4 Flexcomm Interface 4 (USART, SPI, I
2
C, I
2
S) Same as Flexcomm0
19 Flexcomm Interface 5 Flexcomm Interface 5 (USART, SPI,I
2
C, I
2
S). Same as Flexcomm0.
20 Flexcomm Interface 6 Flexcomm Interface 6 (USART, SPI, I
2
C, I
2
S). Same as Flexcomm0.
21 Flexcomm Interface 7 Flexcomm Interface 7 (USART, SPI, I
2
C, I
2
S). Same as Flexcomm0.
22 ADC ADC0 completion. See enable read and set register
of this module.
23 Reserved - -
24 ACMP Comparator Sub-system. See enable read and set register
of this module.
25 Reserved - -
26 Reserved - -
27 USB0_NEEDCLK USB0 activity Interrupt. See enable read and set register
of this module.
28 USB0 USB0 host and device. See enable read and set register
of this module.
29 RTC RTC alarm and wake-up interrupts. See enable read and set register
of this module.
30 Reserved - -
31 MAILBOX System IRQ for Mailbox -
32 PIN_INT4 Pin interrupt 4 or pattern match engine slice 4 int PSTAT - pin interrupt status.
33 PIN_INT5 Pin interrupt 5 or pattern match engine slice 5 int PSTAT - pin interrupt status.
34 PIN_INT6 Pin interrupt 6 or pattern match engine slice 6 int PSTAT - pin interrupt status.
35 PIN_INT7 Pin interrupt 7 or pattern match engine slice 7 int PSTAT - pin interrupt status.
36 CTIMER2 Standard counter/timer CTIMER2 Match and capture interrupts.
37 CTIMER4 Standard counter/timer CTIMER4 Match and capture interrupts.
38 OSEVTIMER OSTIMER0 -
39 Reserved - -
Table 7. Connection of interrupt sources to the NVIC
…continued
Interrupt Name Interrupt description Flags