LPC55S6x嵌入式微控制器用户手册：Arm Cortex-M33与安全特性概览

需积分: 11 90 浏览量更新于2024-07-16 收藏 13.18MB PDF 举报

LPC55S6x是一款基于Arm Cortex-M33架构的嵌入式微控制器，专为高性能和安全应用设计。这款微控制器具有强大的硬件特性，包括最高320kB的片内SRAM和640kB的片内闪存，支持高速和全速USB主机和设备接口，无需外部时钟即可实现全速功能。它还配备了一个SD/MMC/SDIO接口、五个通用定时器、一个SCTimer/PWM、一个RTC/报警定时器、一个24位多速率定时器（MRT）、一个窗口看门狗定时器（WWDT）、一个高速SPI接口（高达50MHz），以及八个灵活的串行通信外设，可以作为USART、SPI、I2C或I2S接口使用。安全性是LPC55S6x的重要卖点，它配备了TrustZone技术，提供隔离保护，确保宝贵知识产权和数据的安全。Cortex-M33内核集成了数字信号处理（DSP）指令，简化了数字信号控制系统的设计和软件开发。为了满足安全需求，该微控制器支持各种加密算法，如哈希（HASH）、AES、RSA、UUID的处理，以及动态加密解密功能。此外，还提供了调试认证和TBSA合规性支持。文档还涵盖了其他关键功能，如电源管理、PLU（Power Logic Unit）、CASPER（嵌入式安全启动模块）、以及用于传感器输入的16位1.0 Msamples/sec的ADC和温度传感器。在文档的系统配置部分（Chapter 4 "LPC55S6x SYSCON"），提供了详细的系统设置选项和更新信息，帮助用户优化设备性能。文档版本历史表明，自2019年发布以来，LPC55S6x User Manual经历了多次迭代，增加了新的功能和改进，以适应不断变化的需求和技术发展。用户在查阅时应注意查看最新的修订版以获取最新信息。 LPC55S6x是一款功能强大、安全性高且高度可扩展的微控制器，适用于需要高效处理、快速通信和高级安全性的各种嵌入式系统项目。开发者可以根据其丰富的特性选择合适的配置，并利用其内置的优化工具和安全特性来构建可靠的产品。

User manual Rev. 1.3 — 10 May 2019 16 of 1148

3.1 How to read this chapter

Available interrupt sources may vary with specific LPC55xx device types.

3.2 Features

• Nested Vectored Interrupt Controller (NVIC) is an integral part of each CPU.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC of the Cortex-M33 supports:

– 64 vectored interrupt slots

– Eight programmable interrupt priority levels with hardware priority level masking.

– Vector table offset register VTOR.

– Software interrupt generation.

– Support for NMI from any interrupt, see Section 21.4.3

3.3 General description

The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient

processing of late arriving interrupts.

3.3.1 Interrupt sources

Tabl e 7 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. The interrupt number does not imply any

interrupt priority when interrupts are not given the same priority. In the case, where two

interrupts for example are given the same priority, then the interrupt number below is

relevant.

See Ref. 1 “

Cortex-M33 DGUG” for detailed descriptions of the NVIC and the NVIC

registers.

UM11126

Chapter 3: LPC55S6x Nested Vectored Interrupt Controller

(NVIC)

Rev. 1.3 — 10 May 2019 User manual

Table 7. Connection of interrupt sources to the NVIC

Interrupt Name Interrupt description Flags

0WDT

BOD

FLASH

Windowed watchdog timer, Brown Out Detect,

Flash controller.

WARNINT - watchdog warning

interrupt

BODINTVAL - BOD interrupt

level.

1 SDMA0 SDMA0 controller. Interrupt A and interrupt B, error

interrupt.

2 GPIO_GLOBALINT0 GPIO group 0. Enabled pin interrupts.

3 GPIO_GLOBALINT1 GPIO group 1. Enabled pin interrupts.

User manual Rev. 1.3 — 10 May 2019 17 of 1148

NXP Semiconductors

UM11126

Chapter 3: LPC55S6x Nested Vectored Interrupt Controller (NVIC)

4 GPIO_INT0_IRQ0 Pin interrupt 0 or pattern match engine slice 0. PSTAT - pin interrupt status.

5 GPIO_INT0_IRQ1 Pin interrupt 1or pattern match engine slice 1. PSTAT - pin interrupt status.

6 GPIO_INT0_IRQ2 Pin interrupt 2 or pattern match engine slice 2. PSTAT - pin interrupt status.

7 GPIO_INT0_IRQ3 Pin interrupt 3 or pattern match engine slice 3. PSTAT - pin interrupt status.

8 UTICK Micro-tick timer. INTR.

9 MRT Multi-rate timer. Global MRT interrupts: GFLAG0,

1, 2, 3.

10 CTIMER0 Standard counter/timer CTIMER0. Match and capture interrupts.

11 CTIMER1 Standard counter/timer CTIMER1. Match and capture interrupts.

12 SCT SCTimer. EVFLAG SCT event.

13 CTIMER3 Standard counter/timer CTIMER3. Match and capture interrupts.

14 Flexcomm Interface 0 Flexcomm Interface 0 (USART, SPI, I

C, I

S). See enable read and set register

of this module

15 Flexcomm Interface 1 Flexcomm Interface 1 (USART, SPI, I

C, I

S).

Same as Flexcomm0.

16 Flexcomm Interface 2 Flexcomm Interface 2 (USART, SPI, I

C, I

S) Same as Flexcomm0

17 Flexcomm Interface 3 Flexcomm Interface 3 (USART, SPI, I

C, I

S) Same as Flexcomm0.

18 Flexcomm Interface 4 Flexcomm Interface 4 (USART, SPI, I

C, I

S) Same as Flexcomm0

19 Flexcomm Interface 5 Flexcomm Interface 5 (USART, SPI,I

C, I

S). Same as Flexcomm0.

20 Flexcomm Interface 6 Flexcomm Interface 6 (USART, SPI, I

C, I

S). Same as Flexcomm0.

21 Flexcomm Interface 7 Flexcomm Interface 7 (USART, SPI, I

C, I

S). Same as Flexcomm0.

22 ADC ADC0 completion. See enable read and set register

of this module.

23 Reserved - -

24 ACMP Comparator Sub-system. See enable read and set register

of this module.

25 Reserved - -

26 Reserved - -

27 USB0_NEEDCLK USB0 activity Interrupt. See enable read and set register

of this module.

28 USB0 USB0 host and device. See enable read and set register

of this module.

29 RTC RTC alarm and wake-up interrupts. See enable read and set register

of this module.

30 Reserved - -

31 MAILBOX System IRQ for Mailbox -

32 PIN_INT4 Pin interrupt 4 or pattern match engine slice 4 int PSTAT - pin interrupt status.

33 PIN_INT5 Pin interrupt 5 or pattern match engine slice 5 int PSTAT - pin interrupt status.

34 PIN_INT6 Pin interrupt 6 or pattern match engine slice 6 int PSTAT - pin interrupt status.

35 PIN_INT7 Pin interrupt 7 or pattern match engine slice 7 int PSTAT - pin interrupt status.

36 CTIMER2 Standard counter/timer CTIMER2 Match and capture interrupts.

37 CTIMER4 Standard counter/timer CTIMER4 Match and capture interrupts.

38 OSEVTIMER OSTIMER0 -

39 Reserved - -

Table 7. Connection of interrupt sources to the NVIC

…continued

Interrupt Name Interrupt description Flags

User manual Rev. 1.3 — 10 May 2019 19 of 1148

NXP Semiconductors

UM11126

Chapter 3: LPC55S6x Nested Vectored Interrupt Controller (NVIC)

3.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

Table 8. Register overview: NVIC (base address = 0xe000e100)

Name Access Offset Description Reset

value

Section

ISER0 R/W 0x100 Interrupt set enable register 0. This register allows enabling interrupts and

reading back the interrupt enables for peripheral functions.

0 3.4.1

ISER1 R/W 0x104 Interrupt set enable register 1. See ISER0 description. 0 3.4.2

ICER0 R/W 0x180 Interrupt clear enable register 0. This register allows disabling interrupts and

reading back the interrupt enables for peripheral functions.

0 3.4.3

ICER1 R/W 0x184 Interrupt clear enable register 1. See ISER0 description. 0 3.4.4

ISPR0 R/W 0x200 Interrupt set pending register 0. This register allows changing the interrupt state

to pending and reading back the interrupt pending state for peripheral functions.

0 3.4.5

ISPR1 R/W 0x204 Interrupt set pending register 1. See ISPR0 description. 0 3.4.6

ICPR0 R/W 0x280 Interrupt clear pending register 0. This register allows changing the interrupt

state to not pending and reading back the interrupt pending state for peripheral

functions.

0 3.4.7

ICPR1 R/W 0x284 Interrupt clear pending register 1. See ICPR0 description. 0 3.4.8

IABR0 RO 0x300 Interrupt active bit register 0. This register allows reading the current interrupt

active state for specific peripheral functions.

0 3.4.9

IABR1 RO 0x304 Interrupt active bit register 1. See IABR0 description. 0 3.4.10

IPR0 R/W 0x400 Interrupt priority register 0. This register contains the 3-bit priority fields for

interrupts 0 to 3.

0 3.4.11

IPR1 R/W 0x404 Interrupt priority register 1. This register contains the 3-bit priority fields for

interrupts 4 to 7.

0 3.4.12

IPR2 R/W 0x408 Interrupt priority register2. This register contains the 3-bit priority fields for

interrupts 8 to 11.

0 3.4.13

IPR3 R/W 0x40C Interrupt priority register 3. This register contains the 3-bit priority fields for

interrupts 12 to 15.

0 3.4.14

IPR4 R/W 0x410 Interrupt priority register 4. This register contains the 3-bit priority fields for

interrupts 16 to 19.

0 3.4.15

IPR5 R/W 0x414 Interrupt priority register 5. This register contains the 3-bit priority fields for

interrupts 20 to 23.

0 3.4.16

IPR6 R/W 0x418 Interrupt priority register 6. This register contains the 3-bit priority fields for

interrupts 24 to 27.

0 3.4.17

IPR7 R/W 0x41C Interrupt priority register 7. This register contains the 3-bit priority fields for

interrupts 28 to 31.

0 3.4.18

IPR8 R/W 0x420 Interrupt priority register 8. This register contains the 3-bit priority fields for

interrupts 32 to 35.

0 3.4.19

IPR9 R/W 0x424 Interrupt priority register 9. This register contains the 3-bit priority fields for

interrupts 36 to 39.

0 3.4.20

IPR10 R/W 0x428 Interrupt priority register 10. This register contains the 3-bit priority fields for

interrupts 40 to 43.

0 3.4.21

IPR11 R/W 0x42C Interrupt priority register 11. This register contains the 3-bit priority fields for

interrupts 44 to 47.

0 3.4.22

IPR12 R/W 0x430 Interrupt priority register 12. This register contains the 3-bit priority fields for

interrupts 48 to 51

0 3.4.23

User manual Rev. 1.3 — 10 May 2019 20 of 1148

NXP Semiconductors

UM11126

Chapter 3: LPC55S6x Nested Vectored Interrupt Controller (NVIC)

3.4.1 Interrupt set-enable register 0

The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the

enabled state of those interrupts. The remaining interrupts are enabled via the ISER1

Interrupt set-enable register 1”. Disabling interrupts is done

through the ICER0 and ICER1 registers Section 3.4.3 “

Interrupt clear enable register 0”

and Section 3.4.4 “

Interrupt clear enable register 1”.

IPR13 R/W 0x434 Interrupt priority register13. This register contains the 3-bit priority fields for

interrupts 52 to 55.

0 3.4.24

IPR14 R/W 0x438 Interrupt priority register14. This register contains the 3-bit priority fields for

interrupts 56 to 60.

0 3.4.25

IPR15 R/W 0x43C Interrupt priority register15. This register contains the 3-bit priority fields for

interrupts 61 to 63.

0 3.4.25

STIR WO 0xF00 Software trigger interrupt register, allows software to generate interrupts. - 3.4.26

Table 8. Register overview: NVIC (base address = 0xe000e100) …continued

Name Access Offset Description Reset

value

Section

Table 9. Interrupt set-enable register 0

Bit Name Value Function

0 ISE_WDTBOD

[1]

Watchdog Timer, BOD interrupt enable.

1 ISE_SDMA0

[1]

SDMA0 interrupt enable.

2 ISE_GINT0

[1]

GPIO group 0 interrupt enable.

3 ISE_GINT1

[1]

GPIO group 1 interrupt enable.

4 ISE_PINT0

[1]

Pin interrupt / pattern match engine slice 0 interrupt enable.

5 ISE_PINT1

[1]

Pin interrupt / pattern match engine slice 1 interrupt enable.

6 ISE_PINT2

[1]

Pin interrupt / pattern match engine slice 2 interrupt enable.

7 ISE_PINT3

[1]

Pin interrupt / pattern match engine slice 3 interrupt enable.

8 ISE_UTICK

[1]

Micro-Tick Timer interrupt enable.

9 ISE_MRT

[1]

Multi-Rate Timer interrupt enable.

10 ISE_CTIMER0

[1]

Standard counter/timer CTIMER0 interrupt enable.

11 ISE_CTIMER1

[1]

Standard counter/timer CTIMER1 interrupt enable.

12 ISE_SCT

[1]

SCT interrupt enable.

13 ISE_CTIMER3

[1]

Standard counter/timer CTIMER3 interrupt enable.

14 ISE_FC0

[1]

Flexcomm Interface 0 interrupt enable.

15 ISE_FC1

[1]

Flexcomm Interface 1 interrupt enable.

16 ISE_FC2

[1]

Flexcomm Interface 2 interrupt enable.

17 ISE_FC3

[1]

Flexcomm Interface 3 interrupt enable.

18 ISE_FC4

[1]

Flexcomm Interface 4 interrupt enable.

19 ISE_FC5

[1]

Flexcomm Interface 5 interrupt enable.

20 ISE_FC6

[1]

Flexcomm Interface 6 interrupt enable.

21 ISE_FC7

[1]

Flexcomm Interface 7 interrupt enable.

22 ISE_ADC0

[1]

ADC0 interrupt enable.

23 Reserved

[1]

24 ISE_ACMP

[1]

ACOMP interrupt enable.

剩余1147页未读，继续阅读

书香度年华

粉丝: 1w+
资源: 383

LPC55S6x嵌入式微控制器用户手册：Arm Cortex-M33与安全特性概览

NXP_LPC55S6x 32-bit Arm Cortex:registered:-M33-综合文档

LPC111x_C1x User manual R3.pdf

LPC17xx User Manual.pdf

LPC408x407x User manual_Rev1.pdf

lpc177x_8x.pdf LPC177x和LPC178X系列数据手册

LPC408X_7X.pdf

LPC178x7x User manual

LPC55S1x_LPC551x Data Sheet中文版.docx

NXP.LPC55S69_DFP.12.0.1.pack

NXP.LPC55S69_DFP.12.1.1.pack

最新资源