TMS320F28x Event Manager 指南：DSP系统关键参考

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"TMS320F28x Event Manager (EV) Reference Guide 是一份由 Texas Instruments 出版的手册，主要关注 TMS320F28x 系列DSP（数字信号处理器）的 Event Manager (EV) 模块。这份指南详细介绍了 EV 模块的功能、使用方法及相关配置，旨在帮助用户理解和利用该模块进行系统设计。" 在 TMS320F28x DSP 系列中，Event Manager (EV) 是一个关键的硬件模块，它负责管理和协调系统中的事件，如中断、定时器和各种输入/输出信号。EV 模块通常用于实时控制应用，如电机控制、电源管理以及工业自动化等领域。以下是对 EV 模块主要特性和功能的详细解释： 1. **事件处理**：EV 模块可以处理多种类型的事件，包括边沿检测、电平检测、比较匹配等。这些事件可以触发中断，从而实现快速响应。 2. **中断管理**：EV 模块提供灵活的中断结构，支持多路中断源，并且可以设置优先级，确保高优先级的事件得到及时处理。 3. **定时器功能**：内置定时器单元可以执行周期性任务或计数操作，适用于时间基准生成、脉冲宽度调制 (PWM) 生成等应用。 4. **PWM 输出**：EV 模块可以生成精确的 PWM 信号，用于电机控制和其他需要模拟信号输出的场合。 5. **同步功能**：通过事件线，EV 模块可以与其他模块（如模数转换器 ADC 或数模转换器 DAC）同步，确保数据采样和转换的准确时机。 6. **配置灵活性**：用户可以通过编程设置 EV 模块的工作模式、触发条件、滤波选项等，以适应不同应用场景的需求。 7. **软件支持**：TI 提供了相应的开发工具和库函数，使得开发者能够轻松地在代码中配置和使用 EV 模块。然而，值得注意的是，TI 对其产品保留随时进行修改、增强、改进的权利，且可能无预警地停止任何产品或服务。因此，在使用 TMS320F28x DSP 及其 EV 模块时，用户应确保获取最新的相关信息，并在下单前验证信息的准确性和完整性。此外，TI 提供的标准保修仅涵盖产品销售时的性能规格，但并不保证所有参数都经过测试。用户有责任确保自己的产品设计和应用程序符合TI器件的要求，TI不对应用援助或客户产品设计的后果承担责任。 TMS320F28x Event Manager 是一个强大的工具，对于需要高效、实时事件处理的嵌入式系统设计者来说，它是不可或缺的一部分。深入理解 EV 模块的特性和操作方式，将有助于开发出更高效、可靠的系统解决方案。

Event Manager Functions

1-7OverviewSPRU065A

compare register for the outputs of the three compare units. The deadband

generation can be enabled/disabled for each compare unit output individually.

The deadband-generator circuit produces two outputs (with or without dead-

band zone) for each compare unit output signal. The output states of the dead-

band generator are configurable and changeable as needed by way of the

double-buffered ACTRx register.

1.1.4 PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by

each event manager: three independent pairs (six outputs) by the three full-

compare units with programmable deadbands, and two independent PWMs

by the GP-timer compares.

1.1.5 PWM Characteristics

Characteristics of the PWMs are as follows:

- 16-bit registers

- Wide range of programmable deadband for the PWM output pairs

- Change of the PWM carrier frequency for PWM frequency wobbling as

needed

- Change of the PWM pulse widths within and after each PWM period as

needed

- External-maskable power and drive-protection interrupts

- Pulse-pattern-generator circuit, for programmable generation of asym-

metric, symmetric, and eight-space vector PWM waveforms

- Minimized CPU overhead using auto-reload of the compare and period

registers

- The PWM pins are driven to a high-impedance state when the PDPINTx

pin is driven low and after PDPINTx signal qualification. The PDPINTx pin

(after qualification) is reflected in bit 8 of the COMCONx register.

J PDPINTA pin status is reflected in bit 8 of COMCONA register.

J PDPINTB pin status is reflected in bit 8 of COMCONB register.

1.1.6 Capture Unit

The capture unit provides a logging function for different events or transitions.

The values of the selected GP timer counter is captured and stored in the two-

Event Manager Functions

Overview1-8 SPRU065A

level-deep FIFO stacks when selected transitions are detected on capture in-

put pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture

unit consists of three capture circuits.

- Capture units include the following features:

J One 16-bit capture control register, CAPCONx (R/W)

J One 16-bit capture FIFO status register, CAPFIFOx

J Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

J Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

J Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one

input pin per capture unit. [All inputs are synchronized with the device

(CPU) clock. In order for a transition to be captured, the input must

hold at its current level to meet two rising edges of the device clock.

The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to

the QEP circuit.]

J User-specified transition (rising edge, falling edge, or both edges)

detection

J Three maskable interrupt flags, one for each capture unit

1.1.7 Quadrature-Encoder Pulse (QEP) Circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can

be used to interface the on-chip QEP circuit with a quadrature encoder pulse.

Full synchronization of these inputs is performed on-chip. Direction or leading-

quadrature pulse sequence is detected, and GP timer 2/4 is incremented or

decremented by the rising and falling edges of the two input signals (four times

the frequency of either input pulse).

1.1.8 External Analog-to-Digital Converter (ADC) Start-of-Conversion

EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC)

for external ADC interface. EVASOC and EVBSOC are muxed with T2CTRIP

and T4CTRIP, respectively.

1.1.9 Power Drive Protection Interrupt (PDPINTx, x = A or B)

The PDPINTx is a safety feature that is provided for the safe operation of sys-

tems such as power converters and motor drives. PDPINTx

can be used to in-

form the monitoring program of motor drive abnormalities such as over-

voltage, over-current, and excessive temperature rise. If the PDPINTx

inter-

Event Manager Functions

1-9OverviewSPRU065A

rupt is unmasked, all PWM output pins will be put in the high-impedance state

immediately after the PDPINTx pin is driven low. An interrupt will also be gen-

erated. See the EXTCONxregister bit function for individual pulse-width modu-

lation (PWM) pair, power protection, or trip functions.

The interrupt flag associated with PDPINTx

is also set when such an event oc-

curs; however, it must wait until the transition on PDPINTx

has been qualified

and synchronized with the internal clock. The qualification and synchroniza-

tion cause a delay of two clock cycles. The setting of the flag does not depend

on whether or not the PDPINTx

interrupt is masked: it happens when a quali-

fied transition occurs on the PDPINTx

pin. This interrupt is enabled following

reset. If the PDPINTx

interrupt is disabled, the action of driving the PWM out-

puts to the high-impedance state (upon a valid PDPINTx interrupt) is also dis-

abled.

1.1.10 EV Registers

The EV registers occupy two 64-word (16-bit) frames of address space. The

EV module decodes the lower six-bits of the address; while the upper 10 bits

of the address are decoded by the peripheral address decode logic, which pro-

vides a module select to the Event Manager when the peripheral address bus

carries an address within the range designated for the EV on that device.

On 28x devices (as with the C240 device), EVA registers are located in the

range 7400h to 7431h. EVB registers are located in the range of 7500h to

7531h.

The undefined registers and undefined bits of the EV registers all return zero

when read by user software. Writes have no effect. See Section 1.3, Event

Manager(EV) Register Addresses, on page 1-12.

1.1.11 EV Interrupts

Each EV interrupt group has multiple interrupt sources, the CPU interrupt re-

quests are processed by the peripheral interrupt expansion (PIE) module. See

the Peripheral Interrupt Expansion Peripheral Reference Guide (literature

number SPRU045) for details. The stages of response are as follows:

1) Interrupt source. If peripheral interrupt conditions occur, the respective

flag bits in registers EVxIFRA, EVxIFRB, or EVxIFRC (x = A or B) are set.

Once set, these flags remain set until explicity cleared by the software. It

is mandatory to clear these flags in the software or future interrupts will not

be recognized.

2) Interrupt enable. The Event Manager interrupts can be individually en-

abled or disabled by interrupt mask registers EVxIMRA, EVxIMRB, and

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