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RTM876-660
Rev0.96
33
PCIE - 7
O
0.8V PCIE “true” differential output.
34
VDD_3.3
P
3.3V power input pin.
PCIE – 8# O 0.8V PCIE “true” differential output.
35
*PCI_STOP#
high
I
3.3V LVTTL PCI_STOP pin
0 = assertion ; 1= de-assertion
PCIE - 8 O 0.8V PCIE “complementary” differential output.
36
*CPU_STOP#
high
I
3.3V LVTTL CPU_STOP pin
0 = assertion ;1= de-assertion
37
VDD_CORE
P
3.3V power input pin.
38
GND_CORE
G
Ground pin.
39
GND
G
Ground pin.
40
CPU - 1#
O
0.8V cpu “complementary” differential output.
41
CPU - 1
O
0.8V cpu “true” differential output.
42
VDD_3.3
P
3.3V power input pin.
43
CPU - 0#
O
0.8V cpu “complementary” differential output.
44
CPU - 0
O
0.8V cpu “true” differential output.
*Vtt_PG#
high
I
3.3V LVTTL Vtt power good input pin low active one- shot function.
0 = assertion
1 = de-assertion
45
*PD
high
I
3.3V LVTTL Vtt power down pin
0 = de-assertion
1= assertion
46
*SDAT
high
I/O
SMBUS serial interface data pin.
47
*SCLK
high
I
SMBUS serial interface clock pin.
48
VDD_3.3
P
3.3V power input pin.
49
XOUT
O
Crystal output pin.
50
XIN
I
Crystal input pin.
51
GND
G
Ground pin.
REF - 2 O 3.3V 14.318MHz output.
52
**MODE
Low
I
3.3V LVTTL CPU_STOP/PCI_STOP function selection pin
0 = PIN34/35 = PCIE-8
1 = PIN34/35 = PCI_STOP/CPU_STOP
**FS_C low
I 1.8V LVTTL frequency selection pin. ., refer to HW latch frequency table
53
REF - 1 O 3.3V 14.318MHz output.
**FS_D low
I 1.8V LVTTL frequency selection pin. ., refer to HW latch frequency table
54
REF - 0 O 3.3V 14.318MHz output.
RESET# O Reset output pin
55
*RESET_IN#
high
I
Reset input pin(only in SiS chipset selection)
0 = assertion
1 = de-assertion
PCI - 0 O 3.3V 33MHz PCI output.
56
**CLKREQ#B
low
I
3.3V LVTTL CLKREQ function selection pin for PCIE4/5(SELECT by CR02[7],CR20[5-4])
0 = pcie free running
1 = CLKREQ stop