"Zynq7020芯片手册Xilinx-XCV405E详解及规格说明"

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The Zynq-7020 is a powerful and versatile chip designed by Xilinx, Inc. The Xilinx-XCV405E is a comprehensive handbook that provides detailed information about the features and specifications of this chip. Released in 2014, the Xilinx-XCV405E manual is a valuable resource for engineers and designers working with the Zynq-7020 chip. One of the key features of the Zynq-7020 chip is its fast and extended block RAM, which operates at 1.8 volts. This FPGA family offers a wide range of capabilities, making it suitable for a variety of applications. The manual includes detailed information about the different modules and components of the chip, as well as production product specifications. It is important to note that the Xilinx-XCV405E manual is now considered obsolete, as it was released in 2014. However, it still serves as a valuable reference for those looking to understand the capabilities and specifications of the Zynq-7020 chip. The manual includes information about Xilinx trademarks, patents, and disclaimers, as well as a disclaimer stating that all specifications are subject to change without notice. Overall, the Xilinx-XCV405E manual provides a comprehensive overview of the Zynq-7020 chip and serves as a valuable resource for engineers and designers working in the field of FPGA technology. It is a testament to the innovation and technology that Xilinx, Inc. is known for, and it highlights the company's commitment to creating high-quality and versatile chips for a wide range of applications.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 2 of 4 www.xilinx.com DS025-2 (v3.0) March 21, 2014

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tions and the desired performance. Finally, the router inter-

connects the blocks.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

The implementation software incorporates Timing Wizard

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

Design Verification

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

TRCE

static timing analyzer.

For in-circuit debugging, an optional download and read-

back cable is available. This cable connects the FPGA in the

target system to a PC or workstation. After downloading the

design into the FPGA, the designer can single-step the

logic, readback the contents of the flip-flops, and so observe

the internal logic state. Simple modifications can be down-

loaded into the system in a matter of minutes.

Configuration

Virtex-E devices are configured by loading configuration

data into the internal configuration memory. Note that

attempting to load an incorrect bitstream causes configura-

tion to fail and can damage the device.

Some of the pins used for configuration are dedicated pins,

while others can be re-used as general purpose inputs and

outputs once configuration is complete.

The following are dedicated pins:

• Mode pins (M2, M1, M0)

• Configuration clock pin (CCLK)

•PROGRAM

• DONE pin

• Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or it can be generated

externally and provided to the FPGA as an input. The

PROGRAM

pin must be pulled High prior to reconfiguration.

Note that some configuration pins can act as outputs. For

correct operation, these pins require a V

CCO

of 3.3 V to per-

mit LVTTL operation. All of the pins affected are in banks 2

or 3. The configuration pins needed for SelectMap (CS,

Write) are located in bank 1.

Configuration Modes

Virtex-E supports the following four configuration modes.

• Slave-serial mode

• Master-serial mode

• SelectMAP mode

• Boundary-scan mode (JTAG)

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Ta bl e 8.

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected. However, it is recom-

mended to drive the configuration mode pins externally.

Tabl e 8: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial D

out

Configuration Pull-ups

Master-serial mode 0 0 0 Out 1 Yes No

Boundary-scan mode 1 0 1 N/A 1 No No

SelectMAP mode 1 1 0 In 8 No No

Slave-serial mode 1 1 1 In 1 Yes No

Master-serial mode 1 0 0 Out 1 Yes Yes

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-2 (v3.0) March 21, 2014 www.xilinx.com Module 2 of 4

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Tabl e 9 lists the total number of bits required to configure

each device.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be set

up at the DIN input pin a short time before each rising edge

of an externally generated CCLK.

For more detailed information on serial PROMs see the

PROM data sheet at

ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed to the DOUT pin.

Data on the DOUT pin changes on the rising edge of CCLK.

The change of DOUT on the rising edge of CCLK differs

from previous families but does not cause a problem for

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex and Virtex-E

only chains.

Figure 13 shows a full master/slave system. A Virtex-E

device in slave-serial mode should be connected as shown

in the right-most device.

Slave-serial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave-serial the default mode if the pins are left

unconnected. However, it is recommended to drive the con-

figuration mode pins externally. Figure 14 shows

slave-serial mode programming switching characteristics.

Tabl e 10 provides more detail about the characteristics

shown in Figure 14. Configuration must be delayed until the

INIT

pins of all daisy-chained FPGAs are High.

Boundary-scan mode 0 0 1 N/A 1 No Yes

SelectMAP mode 0 1 0 In 8 No Yes

Slave-serial mode 0 1 1 In 1 Yes Yes

Tabl e 8: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial D

out

Configuration Pull-ups

Tabl e 9: Virtex-E Bitstream Lengths

Device # of Configuration Bits

XCV405E 3,430,400

XCV812E 6,519,648

Tabl e 10 : Master/Slave Serial Mode Programming Switching

Description

Figure

References Symbol Values Units

CCLK

DIN setup/hold, slave mode

1/2 T

DCC

CCD

5.0/0.0 ns, min

DIN setup/hold, master mode

1/2 T

DSCK

CKDS

5.0/0.0 ns, min

DOUT

CCO

12.0 ns, max

High time

CCH

5.0 ns, min

Low time

CCL

5.0 ns, min

Maximum Frequency

66 MHz, max

Frequency Tolerance, master mode with respect to nominal

+45% –30%

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 2 of 4 www.xilinx.com DS025-2 (v3.0) March 21, 2014

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Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

daisy-chained FPGAs are fast enough to support the clock

rate.

On power-up, the CCLK frequency is approximately

2.5 MHz. This frequency is used until the ConfigRate bits

have been loaded when the frequency changes to the

selected ConfigRate. Unless a different frequency is speci-

fied in the design, the default ConfigRate is 4 MHz.

Figure 13 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The SPROM

RESET

pin is driven by INIT, and the CE input is driven by

DONE. There is the potential for contention on the DONE pin,

depending on the start-up sequence options chosen.

Figure 13: Master/Slave Serial Mode Circuit Diagram

VIRTEX-E

MASTER

SERIAL

VIRTEX-E,

XC4000XL,

SLAVE

XC1701L

PROGRAM

M0 M1

DOUT

CCLK CLK

3.3V

DATA

CEO

RESET/OE

DONE

DIN

INIT

DONE

PROGRAM

CCLK

DIN DOUT

M0 M1

(Low Reset Option Used)

330 Ω

XCVE_ds_013_050103

N/C

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor

of 330 Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω

pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,

DriveDONE should be selected only for the last device in the configuration chain.

Optional Pull-up

Resistor on Done

Figure 14: Slave-Serial Mode Programming Switching Characteristics

CCH

CCO

CCL

CCD

DCC

DIN

CCLK

DOUT

(Output)

X5379_a

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-2 (v3.0) March 21, 2014 www.xilinx.com Module 2 of 4

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The sequence of operations necessary to configure a

Virtex-E FPGA serially appears in Figure 15.

Figure 16 shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Ta bl e 10 shows the timing infor-

mation for Figure 16

At power-up, V

must rise from 1.0 V to V

min in less

than 50 ms, otherwise delay configuration by pulling

PROGRAM

Low until V

is valid.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS

) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE

is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Retention of the SelectMAP port is selectable on a

design-by-design basis when the bitstream is generated. If

retention is selected, PROHIBIT constraints are required to

prevent SelectMAP-port pins from being used as user I/O.

Multiple Virtex-E FPGAs can be configured using the

SelectMAP mode, and be made to start-up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, Data, WRITE

, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS

pin of each device in turn and writing the

appropriate data. See Tabl e 11 for SelectMAP Write Timing

Characteristics.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

not have to complete within one assertion of CS

, illustrated

in Figure 17.

1. Assert WRITE

and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE

must remain

Figure 15: Serial Configuration Flowchart

Apply Power

Set PROGRAM = High

Release INIT

If used to delay

configuration

Load a Configuration Bit

High

Low

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

ds009_15_111799

Configuration Completed

End of

Bitstream?

Yes

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

INIT?

Figure 16: Master-Serial Mode Programming Switching Characteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

DSCK

CKDS

DS022_44_071201

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 2 of 4 www.xilinx.com DS025-2 (v3.0) March 21, 2014

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either asserted or de-asserted. Otherwise an abort is

initiated, as described below.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS

is Low

and WRITE

is High. Similarly, while WRITE is High, no

more that one CS

should be asserted.

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance instead

occurs on the first clock after BUSY goes Low, and the

data must be held until this has happened.

4. Repeat steps 2 and 3 until all the data has been sent.

5. De-assert CS

and WRITE.

A flowchart for the write operation appears in Figure 18.

Note that if CCLK is slower than f

CCNH

, the FPGA never

asserts BUSY, In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

Abort

During a given assertion of CS

, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device remains

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word boundar-

ies, and the FPGA requires a new synchronization word

prior to accepting any new packets.

To initiate an abort during a write operation, de-assert

WRITE

. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 19.

Tabl e 11 : SelectMAP Write Timing Characteristics

Description Symbol Values Units

CCLK

0-7

Setup/Hold 1/2 T

SMDCC

SMCCD

5.0 / 1.7 ns, min

Setup/Hold 3/4 T

SMCSCC

SMCCCS

7.0 / 1.7 ns, min

WRITE

Setup/Hold 5/6 T

SMCCW

SMWCC

7.0 / 1.7 ns, min

BUSY Propagation Delay 7 T

SMCKBY

12.0 ns, max

Maximum Frequency F

66 MHz, max

Maximum Frequency with no handshake F

CCNH

50 MHz, max

Figure 17: Write Operations

DS022_45_071702

CCLK

No Write Write No Write Write

DATA[0:7]

WRITE

BUSY

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