9GHz温度稳健型唤醒接收器：22.3nW功耗与-69.5dBm灵敏度
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"这篇论文介绍了一款微型温度补偿唤醒接收器（WuRX），它在9GHz（X波段）工作时功耗仅为22.3nW（不含温度补偿模块为7.3nW），并且具有良好的温度稳定性。通过将载波频率提升到9GHz并设计一个高阻抗被动包络检测器（ED），使得变压器尺寸减小到0.02cm²，同时仍能实现13.5dB的被动射频电压增益。为了进一步减小面积，采用了全局共模反馈（CMFB）技术，该技术应用于ED和基带放大器，消除了对离芯片AC耦合电容的需求。"
本文重点讨论了微电子领域中的低功耗、高性能的无线通信技术，特别是针对唤醒接收器的设计。文章的核心在于提出了一种创新的温度补偿策略，使得该接收器即使在广泛的温度范围内也能保持其性能稳定，这对于物联网(IoT)设备和远程传感器网络等应用至关重要。
首先，该接收器的工作频率选在9GHz，这是一个相对较高的射频，这一选择的主要目的是减小电路组件的尺寸。通过设计高阻抗的被动包络检测器，可以提高射频信号的处理能力，同时降低功耗。这种设计的变压器在缩小面积的同时，依然保持了足够的增益，这是实现高效能的关键。
其次，全球共模反馈技术的应用是一个显著的优化策略。这一技术能有效地抑制共模噪声，提升信号质量，同时也减少了对外部组件的依赖，降低了系统集成的复杂性和成本。省去了离芯片AC耦合电容，意味着更小的芯片面积和更高的集成度，这对追求低功耗和小型化的现代电子设备具有重要意义。
最后，文章指出，这款22.3nW的唤醒接收器在7.3nW的基础功耗上实现了温度补偿，这表明其在各种环境条件下都能保持良好的工作状态。这对于那些需要在极端或变化的温度环境下运行的设备来说，如工业自动化、环境监测和远程健康监测等应用，是非常有价值的。
这篇文章揭示了如何通过精细的电路设计和创新的温度补偿机制来实现一款高性能、低功耗且温度稳定的唤醒接收器。这项技术对推动未来物联网设备的发展，尤其是那些依赖于超低功耗和可靠通信的设备，有着重要的理论和实践意义。
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
JIANG et al.: 22.3-nW, 4.55 cm
2
TEMPERATURE-ROBUST WURX ACHIEVING A SENSITIVITY OF −69.5 dBm 3
Fig. 3. (a) Simulated waveform output when f
c
/data rate is 0.01 and simu-
lated maximum SNR loss versus (b) f
c
/data rate and (c) code length.
C. BB Circuit Design Challenges
As described in [7], after fixing the architecture and fre-
quency, the only design p arameter that can be traded for
sensitivity is latency. With 20-dBm output power from a
transmitter, better than −65-dBm sensitivity is required to
achieve a reasonable coverage range (∼50 m). To achieve
this sensitivity, a low WuRX data rate (33.3 b/s), a low BB
bandwidth (33.3 Hz), and a long code sequence (18 bit)
are chosen. This results in a latency of 540 ms, which is
acceptable in many, though not all, low-average throughput
IoT applications.
However, the low data rate and the long code sequence
impose a challenge on the conventional ac-coupled BB ampli-
fier [Fig. 1(a)]. Prior work used either nF off-chip capaci-
tors [7] or a 20-pF on-chip capacitor but incurred an SNR
penalty [5]. While the RF components (i.e., antenna and
MN) scale with the carrier frequency, the BB ac-coupling
capacitors are unchanged and only implementable with lumped
components (see Fig. 2).
Fig. 3(a) shows the effect on the signal distortion due to
the ac-coupling. When a signal passes through the high-pass
filter, its dc level shifts toward the bias voltage gradually,
which manifests as a distortion. Since the comparator threshold
voltage is preset to ach ieve the requir ed false-alarm rate and
is constant during the sequence, the signal amplitude with
respect to the threshold voltage decreases with each “1” bit.
The minimum signal amplitude (i.e., the maximum SNR loss)
happens at the end of the last “1” bit. This distortion depends
on the filter corner frequency f
c
and the code (sequence and
length). For example, consider the code consisting of repeating
“10” for simplicity. The maximum SNR loss is plotted against
f
c
normalized to the data rate and code length in Fig. 3(b)
and (c), respectively. The plots show that the distortion is mor e
serious when lower data rates and longer code sequences are
used assuming a fixed f
c
. To bound the distortion to less than
1dB, f
c
must be <0.001× data rate. A similar conclusion
has been drawn in [19, p. 183]. Thus, the 33.3-b/s data rate
needs f
c
≤ 33.3 mHz, which is not possible to reasonably
implement on-chip.
Fig. 4. 9-GHz patch antenna layout.
To address this challenge, dc-coupling should be used
between the ED and BB amplifiers. However, this leads to
issues around biasing (i.e., the preceding stage sets the follow-
ing stage’s operating point) and offset. Section IV proposes an
ED-amplifier co-design scheme where a global CMFB, an AZ
network, and a replica ED are used to address this collectively.
III. RF C
IRCUIT DESIGN
A. Antenna
A patch antenna is a popular choice at high frequency
due to its low cost, high gain, and small form factor that is
compatible with a PCB design. They also have a r elatively nar-
row bandwidth , which is beneficial for interference resilience,
though in some cases, the bandwidth is so narrow that lining
up the antenna’s frequency with the d esired frequency band
and the MN can be difficult. To slightly ease this constraint,
the proposed design employs a conventional patch antenna
next to a pair of parasitic patches, as shown in Fig. 4, which
extends the matching bandwidth from 3% to 5%. The main
patch is 9 × 8.4mm
2
and feeds the following impedance
transformer via a grounded coplanar waveguide (GCPW). The
simulated antenna gain is 5.5 dB.
B. Transformer and Pseudo-Balun ED Co-Design
Prior sub-gigahertz WuRXs utilize discrete components
(inductors and/or MEMS resonators) to implement the MNs
due to their high Q (>100). However, these high-Q passives
become inaccessible as the carrier frequency increases. This
design instead uses distributed components and a bond wire
in the arrangement shown in Fig. 5 to form a transformer. The
T-shaped inductor network (L
1
, L
2
,andL
bond
) is equivalent
to a pair o f coupled inductors. No additional capacitance is
used to avoid extra loss. The ground inductance is carefully
modeled by L
gnd
, as it can significantly affect the performance
at 9 GHz. Specifically, L
gnd
limits the highest operation
frequency since it creates a transmission zero at
f
z,gnd
=
1
2π
L
gnd
C
in
(1)
where C
in
is the ED input capacitance. As shown later, C
in
is
estimated to be 115 fF, and thus, f
z,gnd
should be >15 GHz
so as to not impair the voltage gain at 9 GHz. Thus, L
gnd
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