I2C总线配置：上拉电阻计算与模式解析

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"I2C 总线上的上拉电阻计算方式.pdf" 本文档详细介绍了NXP I2C总线的规范和用户手册，版本为Rev.6，发布于2014年4月4日。I2C（Inter-Integrated Circuit）总线是一种由飞利浦半导体（现为NXP半导体）开发的简单双线双向通信协议，主要用于高效地实现集成电路间的控制。该总线仅需两条线路：串行数据线（SDA）和串行时钟线（SCL）。通过这些线路，可以进行最高达100kbps的Standard模式、400kbps的Fast模式、1Mbps的Fast-mode Plus（Fm+）或3.4Mbps的High-speed模式的数据传输。 I2C总线的特性之一是其上拉电阻的计算，这对系统的稳定性和通信速度至关重要。在I2C总线上，SDA和SCL线通常需要连接到上拉电阻，以保持在没有设备驱动线路时的高电平状态。上拉电阻的选择直接影响数据传输的可靠性和总线的信号质量。上拉电阻的计算需要考虑以下因素： 1. **总线长度**：较长的总线需要更大的上拉电阻来确保足够的上升时间。 2. **总线负载**：每个连接到总线的设备都会增加总线的电容负载，需要足够的上拉电阻来驱动这些负载。 3. **工作速度**：高速模式下，需要更小的上拉电阻以减少信号上升时间，但过小可能导致信号噪声增大。 4. **电源电压**：Vcc的值决定了电阻两端的电压差，需要确保在高电平时能提供足够的电压。一般来说，上拉电阻的典型值范围在4.7kΩ到10kΩ之间。较低的电阻值可以提供更快的上升时间，但会增加功耗和可能的噪声；较高的电阻值可以减少功耗，但可能会导致信号的上升时间变慢，影响通信速度。在实际应用中，工程师还需要考虑系统中的其他因素，如线路的电感、噪声环境以及设备的输入电容等。为了确保兼容性，应遵循I2C规范中推荐的值，并根据具体电路条件进行适当的调整。此外，文档还可能包含关于I2C总线的其他重要信息，如错误检测机制、总线仲裁、时序图、信号电平定义、设备地址分配等。对于需要理解和使用I2C总线的工程师来说，这份手册提供了全面的指导。对于更多详细信息，用户可以通过访问NXP半导体的官方网站（http://www.nxp.com）获取，或者发送电子邮件至salesaddresses@nxp.com查询销售办公室的地址。

User manual Rev. 6 — 4 April 2014 11 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

3.1.7 Clock synchronization

Two masters can begin transmitting on a free bus at the same time and there must be a

method for deciding which takes control of the bus and complete its transmission. This is

done by clock synchronization and arbitration. In single master systems, clock

synchronization and arbitration are not needed.

Clock synchronization is performed using the wired-AND connection of I

C interfaces to

the SCL line. This means that a HIGH to LOW transition on the SCL line causes the

masters concerned to start counting off their LOW period and, once a master clock has

gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see

Figure 7

). However, if another clock is still within its LOW period, the LOW to HIGH

transition of this clock may not change the state of the SCL line. The SCL line is therefore

held LOW by the master with the longest LOW period. Masters with shorter LOW periods

enter a HIGH wait-state during this time.

When all masters concerned have counted off their LOW period, the clock line is released

and goes HIGH. There is then no difference between the master clocks and the state of

the SCL line, and all the masters start counting their HIGH periods. The first master to

complete its HIGH period pulls the SCL line LOW again.

In this way, a synchronized SCL clock is generated with its LOW period determined by the

master with the longest clock LOW period, and its HIGH period determined by the one

with the shortest clock HIGH period.

3.1.8 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more

than one master is used in the system. Slaves are not involved in the arbitration

procedure. A master may start a transfer only if the bus is free. Two masters may

generate a START condition within the minimum hold time (t

HD;STA

) of the START

condition which results in a valid START condition on the bus. Arbitration is then required

to determine which master will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to

see if the SDA level matches what it has sent. This process may take many bits. Two

masters can actually complete an entire transaction without error, as long as the

Fig 7. Clock synchronization during the arbitration procedure

CLK

SCL

counter

reset

wait

state

start counting

HIGH period

mbc632

User manual Rev. 6 — 4 April 2014 12 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

transmissions are identical. The first time a master tries to send a HIGH, but detects that

the SDA level is LOW, the master knows that it has lost the arbitration and turns off its

SDA output driver. The other master goes on to complete its transaction.

No information is lost during the arbitration process. A master that loses the arbitration

can generate clock pulses until the end of the byte in which it loses the arbitration and

must restart its transaction when the bus is free.

If a master also incorporates a slave function and it loses arbitration during the addressing

stage, it is possible that the winning master is trying to address it. The losing master must

therefore switch over immediately to its slave mode.

Figure 8

shows the arbitration procedure for two masters. More may be involved

depending on how many masters are connected to the bus. The moment there is a

difference between the internal data level of the master generating DATA1 and the actual

level on the SDA line, the DATA1 output is switched off. This does not affect the data

transfer initiated by the winning master.

Since control of the I

C-bus is decided solely on the address and data sent by competing

masters, there is no central master, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the

moment when one master sends a repeated START or a STOP condition while the other

master is still sending data. In other words, the following combinations result in an

undefined condition:

• Master 1 sends a repeated START condition and master 2 sends a data bit.

• Master 1 sends a STOP condition and master 2 sends a data bit.

• Master 1 sends a repeated START condition and master 2 sends a STOP condition.

Fig 8. Arbitration procedure of two masters

msc609

DATA

SDA

SCL

master 1 loses arbitration

DATA 1 SDA

User manual Rev. 6 — 4 April 2014 13 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

3.1.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction

cannot continue until the line is released HIGH again. Clock stretching is optional and in

fact, most slave devices do not include an SCL driver so they are unable to stretch the

clock.

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs

more time to store a received byte or prepare another byte to be transmitted. Slaves can

then hold the SCL line LOW after reception and acknowledgment of a byte to force the

master into a wait state until the slave is ready for the next byte transfer in a type of

handshake procedure (see Figure 7

On the bit level, a device such as a microcontroller with or without limited hardware for the

C-bus, can slow down the bus clock by extending each clock LOW period. The speed of

any master is adapted to the internal operating rate of this device.

In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2

3.1.10 The slave address and R/W bit

Data transfers follow the format shown in Figure 9. After the START condition (S), a slave

address is sent. This address is seven bits long followed by an eighth bit which is a data

direction bit (R/W

) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a

request for data (READ) (refer to Figure 10

). A data transfer is always terminated by a

STOP condition (P) generated by the master. However, if a master still wishes to

communicate on the bus, it can generate a repeated START condition (Sr) and address

another slave without first generating a STOP condition. Various combinations of

read/write formats are then possible within such a transfer.

Fig 9. A complete data transfer

1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STOP

condition

START

condition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

mbc604

Fig 10. The first byte after the START procedure

mbc608

R/W

LSBMSB

slave address

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