ADC与DAC转换器规格与性能特性详解

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ADC (Analog-to-Digital Converter) 和 DAC (Digital-to-Analog Converter) 是电子系统中至关重要的信号转换器，它们在通信、信号处理和测量等许多领域扮演着核心角色。本文档主要关注模数转换器（包括 Sampling SAR ADC、Delta-Sigma ADC 和 Pipeline ADC）的规格和性能特点，这些是评估ADC性能的关键指标。 1. **单位增益带宽 (Bandwidth)**: 这个指标定义了ADC在不失真的情况下能够接收的最大频率范围。带宽越高，转换器能处理的高速信号能力越强，适合于需要快速采样的应用。 2. **输入共模范围 (Input Common Mode Range, ICMR)**: 该参数表示输入信号可以安全地落在参考电压中心两侧的范围，超出这个范围可能导致非线性失真或损坏器件。它体现了ADC对输入信号波动的容忍度。 3. **输出摆幅 (Output Swing)**: 表示DAC输出模拟电压的最大变化幅度，直接影响数字信号转化为模拟信号的质量。高输出摆幅意味着转换精度和动态范围更佳。 4. **共模抑制比 (Common Mode Rejection Ratio, CMRR)**: 是衡量ADC抵抗共模噪声干扰的能力，数值越高，说明抑制外部共模信号的能力越强，电路抗干扰性能越好。 5. **极点问题 (Pole)**: 在模数转换过程中，可能会引入极点，即系统的频率响应有下降的部分，这可能会影响转换速度和稳定性。优化设计可以减少或消除极点的影响。 6. **电源抑制比 (Power Supply Rejection Ratio, PSRR)**: 评估ADC对电源电压波动的抑制能力，高的PSRR意味着电源波动对转换结果影响小，提高了系统稳定性。 7. **功耗 (Power Dissipation, Pdiss)**: ADC的能耗是一个重要的考虑因素，特别是在电池供电设备中，低功耗设计至关重要。通过优化架构和电路设计，可以降低功耗，提高转换效率。 8. **踢回噪声 (Thermal Jitter)**: 由于热效应产生的随机噪声，影响了转换器的精度。通过降低工作温度和优化设计，可以减小踢回噪声的影响。 9. **时钟抖动 (Clock Jitter)**: ADC时钟的稳定性直接影响转换结果的准确性和一致性。低时钟抖动是高性能ADC的重要特性。 10. **孔径延时 (Aperture Delay)**: 采样窗口的时间长度，对于连续时间信号的捕捉至关重要。延迟过大可能导致信号丢失，而过小则可能引入噪声。 **流水线ADC (Pipeline ADC)**: 这种ADC架构通过将多个转换步骤并行进行，以提高转换速度，同时保持一定的精度。多级并行处理减少了转换时间，但可能增加复杂性和成本。了解这些关键指标有助于工程师在选择合适的ADC时做出决策，确保系统满足所需的性能和成本效益。在实际设计中，产品数据手册仍然是获取最准确规格和性能参数的最终来源，可以通过Texas Instruments网站获取。

www.ti.com

术语词汇表

：

模数转换的规格和性能特点

ZHCA068-August 2006-Revised January 2008

Submit Documentation Feedback

Glossary of Terms

校正

背景校正法

背景校正法是预先编好程序

，

在转换时不需要进一步的指令就能对预订的频率进行校正

。

在背景校

正法中

，

转换器与输入信号相互断开

，

而在内部进行偏置校正

。

每一类的校正都被存储在转换器内置的

寄存器中

，

并可以在随后的的每次转换中使用

。

转换器的运算法则会在后来的每次转换结果中增加或减

去偏置校正量

，

同时算法也会在每次转换中划分增益校正

。

自校正

接受指令后

，

转换器与外部输入信号断开后即开始自校正

。

一旦自校正开始

，

转换器执行一个内部

偏置或者是增益校正算法

，

其运算法则会在后来的每次转换结果中增加或减去校正偏置量

。

系统校正

接受指令后

，

系统开始自校正

，

同时与外部输入信号相连接

。

在这个模式下

，

转换器可以按照两条

独立的指令进行偏置校正和增益校正

，

包括外部输入信号

。

当转换器的外部输入为零的情况下

，

执行的

是偏置校正

。

它的运算法则会在后来的每次转换结果中增加或减去偏置校正量

。

在转换器的输入为满量

程值的状态下

，

执行的是增益校正

，

同时算法也会在每次转换中划分增益校正

时钟

占空比

时钟信号的占空比是时钟信号在高电平

（

时钟脉冲宽度

）

的时间与时钟周期的时间之比

。

占空比通

常用一个百分数来表示

，

一个完美的方波或微分正弦波的占空比是

50%

。

抖动

A/D

转换器的时钟对采样边沿

（

可以是上升沿或下降沿

，

取决于特定的

A/D

转换器

）

进行计时

，

会产

生标准偏差

。

这种时钟的不稳定性会导致转换误差

，

同时带来转换器噪声的增大

。

转换器的综合抖动包

括孔径抖动和时钟抖动

，

公式为

：

其中

是孔径抖动的均方根

;

是时钟抖动的均方根

孔径抖动和时钟抖动之间没有相互的关联

，

因此这两项可以合并写为一项

，

写成平方和的开方

(rss)

。

通常情况下

，

时钟抖动的影响比

A/D

转换器孔径抖动影响的数倍

，

因此

，

时钟抖动决定了系统的抖

动噪声源

。

同时时钟抖动会对转换器的中频和高频段的信噪比

SNR

产生影响

。

而孔径抖动与采样系统的

时钟抖动结合起来

，

对转换器整个频段的信噪比

SNR

都会产生影响

。

抖动对转换器信噪比

SNR

产生的影

响可以写为

：

•

www.ti.com

t =

+�t )

2 2

SNR�=�20log10(��)

(2 f�t )�

Glossary of Terms

Calibration:

• Background Calibration–

Background calibrations are pre-programmed and occur at a scheduled frequency during converter

operation without further instructions. During a background calibration, the converter is disconnected

from the input signal and an internal offset and/or gain calibration occurs. The results for each

calibration are stored in the internal registers of the converter and applied to every conversion after the

calibration occurs. The converter algorithm subsequently adds or subtracts the offset calibration value

with every conversion result. The converter algorithm also divides the gain calibration value with every

conversion.

• Self-Calibration–

On command, a self-calibration occurs as the converter is disconnected from the input signal. Once

this calibration occurs, the converter performs an internal offset and/or gain calibration algorithm. The

converter algorithm subsequently adds or subtracts the offset calibration value with every conversion

result. The converter algorithm also divides the gain calibration value with every conversion.

• System Calibration–

On command, a system calibration occurs with the input signal connected. In this mode, the converter

calibrates offset and gain, including the external input signal(s), on two separate commands. The offset

calibration is performed with the assumed zero applied to the input of the converter. The converter

algorithm subsequently adds or subtracts the offset calibration value with every following conversion

result. The user can then perform the gain calibration with an assumed full-scale signal applied to the

input. The converter algorithm also divides the gain calibration value with every following conversion.

Clock:

• Duty Cycle–

The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock

pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage value.

The duty cycle of a perfect square wave or a differential sine wave is 50%.

• Jitter–

The standard deviation of clocking the A/D converter sampling edge (can be a rising edge or falling

edge, depending on the specific A/D converter) variation from pulse-to-pulse in time. This instability of

the clock signal may cause converter errors as well as an increase in converter noise.

The total jitter includes both aperture and clock jitter, and is equal to:

Where:

• t

is the root-mean-square of the aperture jitter;

• t

is the root-mean-square of the clock jitter

There is no correlation between the clock-jitter and aperture-jitter terms; therefore, these terms can be

combined on a root-sum-square basis (rss). In most cases, the clock jitter is several times higher than

the A/D converter aperture jitter, making the clock jitter the dominant jitter noise source in the system.

Clock jitter can impact the SNR of the converter at medium and higher frequencies. The aperture jitter,

along with clock jitter of the sampling system, impacts the overall SNR of the conversion. The

contribution of jitter to the SNR of the conversion is equal to:

Where:

• t

is the clock and aperture jitter;

• f is the clock frequency of the converter

• Slew Rate–

The time derivative (δV/δt) of the clock signal (digital input or digital output) as it passes through the

logic, voltage threshold.

6 A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAA147A – August 2006– Revised January 2008

Submit Documentation Feedback

www.ti.com

t =

+�t )

2 2

SNR�=�20log10(��)

(2 f�t )�

Glossary of Terms

Calibration:

• Background Calibration–

Background calibrations are pre-programmed and occur at a scheduled frequency during converter

operation without further instructions. During a background calibration, the converter is disconnected

from the input signal and an internal offset and/or gain calibration occurs. The results for each

calibration are stored in the internal registers of the converter and applied to every conversion after the

calibration occurs. The converter algorithm subsequently adds or subtracts the offset calibration value

with every conversion result. The converter algorithm also divides the gain calibration value with every

conversion.

• Self-Calibration–

On command, a self-calibration occurs as the converter is disconnected from the input signal. Once

this calibration occurs, the converter performs an internal offset and/or gain calibration algorithm. The

converter algorithm subsequently adds or subtracts the offset calibration value with every conversion

result. The converter algorithm also divides the gain calibration value with every conversion.

• System Calibration–

On command, a system calibration occurs with the input signal connected. In this mode, the converter

calibrates offset and gain, including the external input signal(s), on two separate commands. The offset

calibration is performed with the assumed zero applied to the input of the converter. The converter

algorithm subsequently adds or subtracts the offset calibration value with every following conversion

result. The user can then perform the gain calibration with an assumed full-scale signal applied to the

input. The converter algorithm also divides the gain calibration value with every following conversion.

Clock:

• Duty Cycle–

The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock

pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage value.

The duty cycle of a perfect square wave or a differential sine wave is 50%.

• Jitter–

The standard deviation of clocking the A/D converter sampling edge (can be a rising edge or falling

edge, depending on the specific A/D converter) variation from pulse-to-pulse in time. This instability of

the clock signal may cause converter errors as well as an increase in converter noise.

The total jitter includes both aperture and clock jitter, and is equal to:

Where:

• t

is the root-mean-square of the aperture jitter;

• t

is the root-mean-square of the clock jitter

There is no correlation between the clock-jitter and aperture-jitter terms; therefore, these terms can be

combined on a root-sum-square basis (rss). In most cases, the clock jitter is several times higher than

the A/D converter aperture jitter, making the clock jitter the dominant jitter noise source in the system.

Clock jitter can impact the SNR of the converter at medium and higher frequencies. The aperture jitter,

along with clock jitter of the sampling system, impacts the overall SNR of the conversion. The

contribution of jitter to the SNR of the conversion is equal to:

Where:

• t

is the clock and aperture jitter;

• f is the clock frequency of the converter

• Slew Rate–

The time derivative (δV/δt) of the clock signal (digital input or digital output) as it passes through the

logic, voltage threshold.

6 A Glossary of Analog-to-Digital Specifications and Performance Characteristics SBAA147A – August 2006– Revised January 2008

Submit Documentation Feedback

其中

是时钟抖动和孔径抖动

;

是转换器的时钟频率

转换速率

在时钟信号

（

可以是数字信号输入或输出

）

超过逻辑阈值电压时

，

时钟信号的时间导数

。

•

www.ti.com

术语词汇表

：

模数转换的规格和性能特点

ZHCA068-August 2006-Revised January 2008

Submit Documentation Feedback

Glossary of Terms

www.ti.com

000

Analog�Input�Voltage

001

010

011

100

101

110

111

Digital

Output

Code

FS1/2�FS 3/4�FS1/4�FS0

Transition�point =�where

output�code�changes

from�one�code

to�an�adjacent�code

Ideal�transfer�function

for�a�3-bit�A/D

Transition

Points

code�width

Ideal�code�width =

1LSB

000

AnalogInput

001

010

011

100

101

110

111

DigitalOutput

FS1/2�FS

Code

under�test

50%

100%

Transition�point;�uncertainty�noise

Center�of�code�width

Low�side�transition

f K��=�f N

S t

� �

Glossary of Terms

Code Width: The code width is the voltage differential between two adjacent transition points of an A/D

converter digital output code. The code width is ideally equal to 1LSB. See Figure 6.

NOTE: The unipolar ideal transfer function has zero Offset Error, zero Gain Error, zero DNL error, and zero INL error.

In this graph, FS means Full-Scale.

Figure 6. Unipolar Ideal Transfer Function

Code Transition Point (Uncertainty): The Code Transition Point is the point at which the digital output

switches from one code to the next as a result of a changing analog input voltage. The uncertainty or

variation in the transition point is a result of internal converter noise, as Figure 7 illustrates.

Figure 7. A/D Converter Transition Noise

Coherent sampling: Coherent sampling exists when the sampling frequency times the integer number of

cycles of the waveform in the data record equals the frequency of the waveform times the number of

samples in the data record, where the waveform is periodic. In other words, coherent sampling exists

when the following relationship is met:

Where:

• f

= the sampling frequency

• K = number of cycles of a waveform in the data record (integer)

• f

= the waveform frequency

• N = number of samples in the data record

SBAA147A– August 2006 –Revised January 2008 A Glossary of Analog-to-Digital Specifications and Performance Characteristics 7

Submit Documentation Feedback

码元宽度

是

A/D

转换器数字输出的相邻转换点电压宽度

。

理论上码元宽度等于一个最低有效位

LSB

。

见图

注意

：

具有零偏移误差

，

零增益误差

，

零

DNL

误差和零

INL

误差

。

图

单极理想传输函数

码元转换点（不确定性）：

当模拟输入变化时

，

转换器的数字信号输出也随着变化

，

从一个代码跳变到另一

个代码

，

其中的跳变点就是码元转换点

。

而转换器的内部噪声导致了码元转换点的不确定性

，

或者叫抖动

，

如图

所示

。

www.ti.com

000

Analog�Input�Voltage

001

010

011

100

101

110

111

Digital

Output

Code

FS1/2�FS 3/4�FS1/4�FS0

Transition�point =�where

output�code�changes

from�one�code

to�an�adjacent�code

Ideal�transfer�function

for�a�3-bit�A/D

Transition

Points

code�width

Ideal�code�width =

1LSB

000

AnalogInput

001

010

011

100

101

110

111

DigitalOutput

FS1/2�FS

Code

under�test

50%

100%

Transition�point;�uncertainty�noise

Center�of�code�width

Low�side�transition

f K��=�f N

S t

� �

Glossary of Terms

Code Width: The code width is the voltage differential between two adjacent transition points of an A/D

converter digital output code. The code width is ideally equal to 1LSB. See Figure 6.

NOTE: The unipolar ideal transfer function has zero Offset Error, zero Gain Error, zero DNL error, and zero INL error.

In this graph, FS means Full-Scale.

Figure 6. Unipolar Ideal Transfer Function

Code Transition Point (Uncertainty): The Code Transition Point is the point at which the digital output

switches from one code to the next as a result of a changing analog input voltage. The uncertainty or

variation in the transition point is a result of internal converter noise, as Figure 7 illustrates.

Figure 7. A/D Converter Transition Noise

Coherent sampling: Coherent sampling exists when the sampling frequency times the integer number of

cycles of the waveform in the data record equals the frequency of the waveform times the number of

samples in the data record, where the waveform is periodic. In other words, coherent sampling exists

when the following relationship is met:

Where:

• f

= the sampling frequency

• K = number of cycles of a waveform in the data record (integer)

• f

= the waveform frequency

• N = number of samples in the data record

SBAA147A– August 2006 –Revised January 2008 A Glossary of Analog-to-Digital Specifications and Performance Characteristics 7

Submit Documentation Feedback

图

7. A/D

转换器的转换点噪声

相干采样：

当满足以下条件时产生相干采样

，

即采样频率乘以数据记录中波形的整数个周期等于波形的频率

乘以数据记录中的采样数

，

其中的波形是周期性的

。

换句话说

，

只有当满足下式的情况下才会有相干采样

。

www.ti.com

000

Analog�Input�Voltage

001

010

011

100

101

110

111

Digital

Output

Code

FS1/2�FS 3/4�FS1/4�FS0

Transition�point =�where

output�code�changes

from�one�code

to�an�adjacent�code

Ideal�transfer�function

for�a�3-bit�A/D

Transition

Points

code�width

Ideal�code�width =

1LSB

000

AnalogInput

001

010

011

100

101

110

111

DigitalOutput

FS1/2�FS

Code

under�test

50%

100%

Transition�point;�uncertainty�noise

Center�of�code�width

Low�side�transition

f K��=�f N

S t

� �

Glossary of Terms

Code Width: The code width is the voltage differential between two adjacent transition points of an A/D

converter digital output code. The code width is ideally equal to 1LSB. See Figure 6.

NOTE: The unipolar ideal transfer function has zero Offset Error, zero Gain Error, zero DNL error, and zero INL error.

In this graph, FS means Full-Scale.

Figure 6. Unipolar Ideal Transfer Function

Code Transition Point (Uncertainty): The Code Transition Point is the point at which the digital output

switches from one code to the next as a result of a changing analog input voltage. The uncertainty or

variation in the transition point is a result of internal converter noise, as Figure 7 illustrates.

Figure 7. A/D Converter Transition Noise

Coherent sampling: Coherent sampling exists when the sampling frequency times the integer number of

cycles of the waveform in the data record equals the frequency of the waveform times the number of

samples in the data record, where the waveform is periodic. In other words, coherent sampling exists

when the following relationship is met:

Where:

• f

= the sampling frequency

• K = number of cycles of a waveform in the data record (integer)

• f

= the waveform frequency

• N = number of samples in the data record

SBAA147A– August 2006 –Revised January 2008 A Glossary of Analog-to-Digital Specifications and Performance Characteristics 7

Submit Documentation Feedback

其中

采样频率

K =

数据记录中的波形的周期数

(

整数

)

波形的频率

N =

数据记录中的采样数

•

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