STIL标准测试接口语言IEEESTD1450-1999

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STIL标准测试接口语言IEEE STD 1450-1999是由美国电气和电子工程师协会（IEEE）制定的一项标准，用于定义测试系统和芯片设计之间的通信接口。这项标准旨在提供一种标准化的测试语言，以便在不同的测试系统和芯片设计之间实现互操作性。STIL标准测试接口语言IEEE STD 1450-1999的发布日期为1999年9月1日，其打印版的ISBN号为0-7381-1646-7，PDF版的ISBN号为0-7381-1647-5。按照版权声明，STIL标准测试接口语言IEEE STD 1450-1999的版权归美国电气和电子工程师协会所有，未经出版者的事先书面许可，任何部分均不得以任何形式在任何电子检索系统或其他方式中复制。该标准的制定旨在解决测试系统和芯片设计之间的通信接口问题。测试系统需要能够与不同的芯片设计进行通信，并能够准确地执行测试程序，以验证芯片的性能和功能。然而，不同的测试系统和芯片设计通常使用不同的测试语言和接口协议，这导致了互操作性和兼容性方面的问题。 STIL标准测试接口语言IEEE STD 1450-1999的出台就是为了解决这些问题。它定义了一种通用的测试语言，可以用于描述测试程序和测试模式，以及测试系统和芯片设计之间的通信接口。通过采用这一标准，不同的测试系统和芯片设计可以使用相同的测试语言和接口协议，从而实现互操作性和兼容性。该标准包括了语法和语义规范，以及与测试系统和芯片设计相关的其他规范。它还提供了一个标准库，包含了一系列常用的测试模式和测试程序，可以满足大多数测试需求。此外，该标准还提供了一套标准的接口协议，用于测试系统和芯片设计之间的通信。这些规范和工具的统一性和标准化程度，有助于降低测试系统和芯片设计之间的集成和兼容性风险。 STIL标准测试接口语言IEEE STD 1450-1999的制定得到了广泛的行业支持。它已经成为了一种行业标准，被广泛地应用于各种芯片设计和测试系统中。许多厂商和设计者都在其产品中采用了这一标准，以便与其他厂商的产品实现互操作性和兼容性。除了在工业界的应用外，STIL标准测试接口语言IEEE STD 1450-1999还在学术界得到了广泛的关注。许多学术界的研究人员和教育者都使用这一标准进行研究和教学，以便培养更多的与实际需求相符的人才。总的来说，STIL标准测试接口语言IEEE STD 1450-1999为测试系统和芯片设计之间的通信接口问题提供了一种标准化的解决方案。它的出台对于推动测试系统和芯片设计之间的互操作性和兼容性发挥了重要作用，对于推动整个产业的发展也起到了积极的促进作用。通过采用这一标准，行业能够更好地满足用户需求，加速产品的创新和迭代开发，从而推动整个产业的进步和发展。

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IEEE

Std 1450-1999 IEEE STANDARD TEST INTERFACE LANGUAGE (STIL)

In the syntax explanations, the verb “shall” is used to indicate mandatory requirements. The meaning of a

mandatory requirement varies for different readers of the standard:

— To developers of tools that process STIL (“readers”), “shall” denotes a requirement that the standard

imposes. The resulting implementation is required to enforce this requirement and issue an error if

the requirement is not met by the input.

— To developers of STIL ﬁles (“writers”), “shall” denotes mandatory characteristics of the language.

The resulting output must conform to these characteristics.

— To the users of STIL, “shall” denotes mandatory characteristics of the language. Users may depend

on these characteristics for interpretation of the STIL source.

The language deﬁnition clauses contain statements that use the phrase “it is an error,” and “it may be ambig-

uous.” These phrases indicate improperly-deﬁned STIL information. The interpretation of these phrases will

differ for the different readers of this standard in the same way that “shall” differs , as identiﬁed in the

dashed list above (Clause 4).

Waveforms represented in the diagrams use symbols deﬁned in Table 9 through Table 12. Use the informa-

tion in these tables to help understand waveform diagrams.

5. STIL orientation and capabilities tutorial (informative)

This clause presents an overview of STIL through a layered tutorial that explains the language constructs.

This clause is informative and is not a part of IEEE Std 1450-1999, Standard Test Interface Language (STIL)

for Digital Test Vector Data.

5.1 Hello Tester

Figure 3 represents a complete STIL program to exercise a subset of behavior for an octal bus transceiver

design, modeled after a TTL LS245. Details of this design are found in Annex E. This example deﬁnes the

LS245 as “unidirectional.” To simplify this example, the “A” bus signals are deﬁned as inputs, and the “B”

bus signals are deﬁned as outputs. Figure 3 is annotated and explanations (notes) for each of the marked sec-

tions follow the ﬁgure.

NOTE—Figure notes follow all of the annotated ﬁgures in this standard.

IEEE

Std 1450-1999 IEEE STANDARD TEST INTERFACE LANGUAGE (STIL)

Notes for Figure 3.

NOTE 1—The very ﬁrst statement in a STIL ﬁle is the

STIL

statement. This statement deﬁnes the version of the STIL

language following this statement.

NOTE 2—The

Signals

block deﬁnes a name for each signal used in the test vectors and identiﬁes the signal type, such as

In, Out, InOut, Supply, or Pseudo. Remember that in this example the bidirectional busses of the LS245 design are

deﬁned as unidirectional and, therefore, only In and Out are used here.

NOTE 3—The SignalGroups block deﬁnes an ordered set of signals to be referenced in subsequent operations. In this

example, three groups are deﬁned: a collection of all bits of the “A” bus, called ABUS; a collection of all bits of the “B”

bus, called BBUS; and a collection of all signals in the design called ALL. ALL has been deﬁned using the two previous

group deﬁnitions. The operators “+” and “-” are used to deﬁne these ordered groups in objects called “pin expressions.”

NOTE 4—The Timing block deﬁnes sets of “WaveformTables.” Each WaveformTable deﬁnes the waveforms to be

applied to each signal used in a vector. After the Timing keyword is the quoted string “Hello Tester Timing.” This quoted

string becomes the name of this Timing block. By enclosing the name with double-quotes, characters such as spaces can

be made to be part of the name.

NOTE 5—The ﬁrst statement in a WaveformTable is the period of the test vector to be applied to all signals. All signals

deﬁned in a single WaveformTable must have the same period. In this example, the tester period is 500 ns long.

Each signal may have several different waveforms deﬁned in a single WaveformTable. Each waveform deﬁned for a sig-

nal will be referenced with a single character, called a WaveformChar, or “WFC.” Within each WaveformTable, each sig-

nal’s WaveformChars must be unique across all waveforms deﬁned for the signal. However, different signals may deﬁne

the same WaveformChar for different waveforms.

A waveform needs some explanation. In STIL, a waveform is a series of “time” and “event” pairs. Each pair is deﬁned

with a single STIL statement; these statements are also referred to as “timed events.” The “event” may be a special single

character deﬁned to have a particular operation, or it may be a longer identiﬁer as used in this example. This example

used the events “ForceDown,” “ForceUp,” “ForceOff,” “CompareUnknown,” “CompareHighWindow,” “CompareLow-

Window,” and “CompareOffWindow.” “ForceDown” and “ForceUp” are input or drive events; “ForceDown” forces a

logic low on an input, and “ForceUp” forces a logic high. “ForceOff” forces a logic ﬂoat-state, or turns off any input

drivers. “CompareHighWindow,” “CompareLowWindow,” “CompareOffWindow,” and “CompareUnknown” are output,

or expect, events. “CompareHighWindow” expects a logic high, “CompareLowWindow” expects a logic low, and “Com-

pareOffWindow” expects a logic ﬂoat-state value. To close a window strobe, the event “CompareUnknown” is used.

There are four distinct types of signals in this design. Each has its own waveform to represent the input or output infor-

mation required to test this design.

NOTE 6—The ﬁrst waveform deﬁnition is for the signal DIR. This signal controls the “direction” of the bused signals,

which is ﬁxed in this test. Even though it is ﬁxed, information is deﬁned for signal DIR to allow this signal to be driven

high or driven low at the start of each test cycle. Figure 4 shows graphically the two waveforms deﬁned for this signal

and the STIL syntax.

Because both waveforms have the same timing, they can be merged into a single STIL statement. This shorthand syntax

allows multiple WaveformChars to be deﬁned to the same event in the waveform, with states for each WaveformChar to

apply at that time. The relationship of WaveformChar to event characters is direct: the ﬁrst WaveformChar (in the exam-

ple above, “0”) maps to the ﬁrst waveform event (“ForceDown”), the second (“1”) maps to the second event

(“ForceUp”), and so on for each WaveformChar present. Note that a slash must be present to separate the event refer-

ences when more than one is present.

The signal OE_ has additional events deﬁned to create a pulsed behavior. The merging process for this signal is not as

intuitive as DIR, as the process here requires deﬁning events that do not cause a change of state on the signal. The only

reason to deﬁne these events is to support a single waveform deﬁnition for this signal.

The ABUS signals are deﬁned similarly to DIR, except that they are offset 10 ns into the vector boundary. Note the use

of a Group here to reference a collection of signals to be deﬁned.

The BBUS signals are deﬁned as outputs; at entry to the cycle, any test drivers are explicitly turned off with the

“ForceOff” event. The WaveformChar characters H, L and Z are mapped to the expected states “CompareHighWindow,”

IEEE

FOR DIGITAL TEST VECTOR DATA Std 1450-1999

“CompareLowWindow,” and “CompareOffWindow,” respectively. The strobe window is opened at 260 ns. At 280 ns, the

strobe is closed with an “CompareUnknown” event.

NOTE 7—STIL supports two styles of comments: “block comments,” which are delimited by a “/*” and “*/”, and “com-

ments to the newline,” which are delimited by a “//” and terminated with a newline. The comments annotating the clos-

ing braces in this example use the style of comments to the newline.

NOTE 8—The PatternBurst block deﬁnes a collection of pattern names to be executed sequentially. (In this example,

there is only one pattern deﬁned.) All patterns deﬁned in a single PatternBurst are executed under a similar context, the

context being deﬁned by the subsequent PatternExec statement. The references to pattern names in this block are one of

the few forward references allowed in STIL; patterns are not deﬁned until the end of the STIL data.

NOTE 9—The PatternExec block deﬁnes how PatternBurst and Timing information is assembled to create the set of

tests to execute. The references in this block to Timing and PatternBurst names must have been deﬁned before this block.

NOTE 10—Finally, the pattern data is deﬁned. Pattern data constitutes the bulk of data in the STIL data set, and is gen-

erally processed one-vector-at-a time. In order to support processing this data as it is read, it is necessary to deﬁne pat-

tern data as the last data in a STIL test environment.

In this example, the ﬁrst statement in the Pattern block is a reference to a WaveformTable; the following vectors (until

another ‘W’ statement) will use the timing deﬁned in the WaveformTable named “one.”

Note that while this pattern contains references to WaveformChars, and to names of WaveformTables, it does not contain

any direct references to the Timing block. This resolution is provided by the PatternExec statement. The PatternExec can

deﬁne references to different Timing blocks; as long as the WaveformChars and WaveformTable names are deﬁned in the

referenced timing set, they can be applied to these same patterns.

Each V statement deﬁnes one test vector. In this example, each Vector deﬁnes the state to be applied to each signal using

the group reference ALL. The declaration order of signals in the group ALL is critical, as the mapping of Waveform-

Chars to signals in the group is performed linearly.

DIR { 01 { ’0ns’ ForceDown/ForceUp; }}

DIR { 0 { ’0ns’ ForceDown; }}

DIR { 1 { ’0ns’ ForceUp; }}

T0 T0

ForceUp at start of vector (at T0)

ForceDown at start of vector (at T0)

500ns

Waveforms to be defined for signal DIR:

STIL syntax to generate these waveforms

These two STIL statements can be merged

into the single statement:

Figure 4—Waveforms associated with signal DIR

一一对应

IEEE

Std 1450-1999 IEEE STANDARD TEST INTERFACE LANGUAGE (STIL)

5.1.1 STIL grammatical constructs

STIL has two basic grammatical constructs for statements in the language. The ﬁrst is a “simple statement,”

featuring a keyword, zero or more other tokens, and terminated by a semicolon. The second is a “block state-

ment,” which again starts with a keyword, may again be followed by zero or more tokens, and then has an

open-brace. After the open-brace, additional STIL language statements may occur. This statement is termi-

nated by a closing brace. These two statement formats are shown in Figure 6.

Figure 6 is intended to represent a simpliﬁcation of the STIL syntax. Some statements, such as the assign-

ment statements in Figure 3 (ALL=0000000000LLLLLLLL), also require the “=” sign to be present.

STIL is a case-sensitive language. All STIL keywords start with an uppercase letter, and some may have

additional uppercase letters inside.

5.1.2 Complexity and language subsets

The previous example of STIL data has been reduced to present the basic language constructs only. As this

tutorial progresses through additional examples, different aspects of the STIL language will be presented.

There are many ways in which digital test information may be developed or provided. Some types of tests

may be more concerned about testing device speciﬁcations. Such tests may not care about how the device

OE_ { 01 {’0ns’ ForceUp;

’200ns’ ForceDown/ForceUp;

’300ns’ ForceUp;}}

OE_ { 0 { ’0ns’ ForceUp; ’200ns’

ForceDown; ’300ns’ ForceUp; }}

OE_ { 1 { ’0ns’ ForceUp; ’200ns’

ForceUp; ’300ns’ ForceUp; }}

Waveforms to be defined for signal OE_:

T0 T0

ForceUp at start of vector

500ns

(ForceUp at 200 ns)

(ForceUp at 300 ns)

ForceUp at start of vector

ForceDown at 200 ns after T0

ForceUp at 300 ns after T0

STIL syntax to generate these waveforms:

The value of the repeated events in the

second waveform only becomes apparent

after the merging of these two statements:

Figure 5—Waveforms associated with the signal OE_

Keyword (OPTIONAL_TOKENS)*;

Keyword (OPTIONAL_TOKENS)* { (OPTIONAL_MORE_STATEMENTS)* }

Simple statement:

Block statement:

Figure 6—STIL statement structure

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