VHDL编程实践指南第四版

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"VHDL Programming by Example 4th Ed - Douglas L. Perry" VHDL（Very High-Speed Integrated Circuit Hardware Description Language）是一种广泛应用于数字电路设计的硬件描述语言。本书《VHDL Programming by Example 4th Ed》是Douglas L. Perry编著的第四版，旨在通过实例教授读者如何使用VHDL进行设计和仿真。在VHDL编程中，了解基本语法和结构是至关重要的。VHDL允许设计师以行为和结构两种方式描述数字系统，这使得它既适用于高层次的功能建模，也适用于低层次的逻辑门级描述。书中的实例将涵盖这些方面，帮助读者掌握VHDL的核心概念。 1. **VHDL的基本元素**： - **实体（Entity）**：定义硬件接口，包括输入、输出以及时钟信号等。 - **架构（Architecture）**：描述实体的内部工作，包括逻辑电路的实现。 - **库（Library）**：包含预定义的组件和数据类型，如IEEE库，其中包含了标准逻辑函数和数据类型。 - **包（Package）**：用于封装常用的数据类型和函数，提高代码的复用性。 - **进程（Process）**：模拟硬件中的并发操作，用于描述时序逻辑。 2. **VHDL的设计流程**： - **设计规格**：明确电路功能和性能需求。 - **编写VHDL代码**：根据规格创建实体和架构，描述电路行为。 - **仿真**：使用VHDL测试平台进行功能验证，检查设计是否满足预期。 - **综合**：将VHDL代码转换为具体的门级电路，这一过程可能涉及优化以减小面积或提高速度。 - **布局与布线**：在特定的 FPGA 或 ASIC 上分配物理资源并连接电路。 - **验证与调试**：在硬件上测试最终设计，确保其在实际环境中的正确性。 3. **VHDL的实例应用**： - **数字逻辑门**：例如AND、OR、NOT等基本逻辑门的描述。 - **计数器**：如模N计数器、二进制计数器和同步/异步计数器。 - **移位寄存器**：左移、右移和循环移位等操作。 - **加法器**：从半加器到多位全加器的实现。 - **状态机**：用于控制序列操作的有限状态机设计。 - **数据转换器**：如模数转换器（ADC）、数模转换器（DAC）的描述。 - **存储器**：ROM、RAM和FIFO的VHDL实现。 4. **VHDL的高级特性**： - **类型和子类型**：定义自定义数据类型，增强代码的可读性和灵活性。 - **数组**：用于表示并行数据处理的多个元素。 - **记录**：类似结构体的数据类型，可以组合多种数据类型。 - **包和子程序**：提高代码模块化和重用性。 - **异常处理**：在设计中加入错误检测和处理机制。 5. **VHDL的仿真工具**： - **ModelSim**：流行的仿真工具，支持VHDL和Verilog。 - **GHDL**：开源的VHDL仿真器。 - **Icarus Verilog**：虽主要针对Verilog，但也可用于VHDL仿真。通过这本书，读者不仅可以学习到VHDL的基本语法，还能深入了解如何使用VHDL进行实际的设计工作，从而为电子工程和计算机科学领域的专业人员提供宝贵的实践指导。

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PREFACE

This is the fourth version of the book and this version now not only provides

VHDL language coverage but design methodology information as well. This

version will guide the reader through the process of creating a VHDL

design, simulating the design, synthesizing the design, placing and routing

the design, using VITAL simulation to verify the final result, and a new

technique called At-Speed debugging that provides extremely fast design

verification. The design example in this version has been updated to reflect

the new focus on the design methodology.

This book was written to help hardware design engineers learn how to

write good VHDL design descriptions. The goal is to provide enough VHDL

and design methodology information to enable a designer to quickly write

good VHDL designs and be able to verify the results. It will also attempt

to bring the designer with little or no knowledge of VHDL, to the level of

writing complex VHDL descriptions. It is not intended to show every pos-

sible construct of VHDL in every possible use, but rather to show the de-

signer how to write concise, efficient, and correct VHDL descriptions of

hardware designs.

This book is organized into three logical sections. The first section of the

book will introduce the VHDL language, the second section walks through

a VHDL based design process including simulation, synthesis, place and

route, and VITAL simulation; and the third section walks through a design

example of a small CPU design from VHDL capture to final gate-level

implementation, and At-Speed debugging. At the back of the book are

included a number of appendices that contain useful information about the

language and examples used throughout the book.

In the first section VHDL features are introduced one or more at a time.

As each feature is introduced, one or more real examples are given to show

how the feature would be used. The first section consists of Chapters 1

through 8, and each chapter introduces a basic description capability of

VHDL. Chapter 1 discusses how VHDL design relates to schematic based

design, and introduces the basic terms of the language. Chapter 2 describes

some of the basic concepts of VHDL, including the different delay mecha-

nisms available, how to use instance specific data, and defines VHDL dri-

vers. Chapter 2 discusses concurrent statements while Chapter 3 introduces

the reader to VHDL sequential statements. Chapter 4 talks about the wide

Preface

xvi

range of types available for use in VHDL. Examples are given for each of

the types showing how they would be used in a real example. In Chapter

5 the concepts of subprograms and packages are introduced. The different

uses for functions are given, as well as the features available in VHDL

packages.

Chapter 6 introduces the five kinds of VHDL attributes. Each attribute

kind has examples describing how to use the specific attribute to the

designer’s best advantage. Examples are given which describe the pur-

pose of each of the attributes.

Chapters 7 and 8 will introduce some of the more advanced VHDL

features to the reader. Chapter 7 discusses how VHDL configurations

can be used to construct and manage complex VHDL designs. Each of

the different configuration styles are discussed along with examples

showing usage. Chapter 8 introduces more of the VHDL advanced top-

ics with discussions of overloading, user defined attributes, generate

statements, and TextIO.

The second section of the book consists of Chapters 9 through 11. Chap-

ters 9 and 10 discuss the synthesis process and how to write synthesiz-

able designs. These two chapters describe the basics of the synthesis

process including how to write synthesizeable VHDL, what is a technol-

ogy library, what does the synthesis process look like, what are con-

straints and attributes, and what does the the optimization process look

like. Chapter 11 discusses the complete high level design flow from VHDL

capture through VITAL simulation.

The third section of the book walks through a description of a small

CPU design from the VHDL capture through simulation, synthesis, place

and route, and VITAL simulation. Chapter 12 describes the top level of

the CPU design from a functional point of view. In Chapter 13 the RTL

description of the CPU is presented and discussed from a synthesis point

of view. Chapter 14 begins with a discussion of VHDL testbenches and

how they are used to verify functionality. Chapter 14 finishes the discus-

sion by describing the simulation of the CPU design. In Chapter 15 the

verified design is synthesized to a target technology. Chapter 16 takes

the synthesized design and places and routes the design to a target

device. Chapter 17 begins with a discussion of VITAL and ends with the

VITAL simulation of the placed and routed CPU design. Chapter 18 is a

new chapter that discusses the new technique of At-Speed debugging.

This chapter provides the reader with an in-depth look at how a hardware

implementation of the CPU design can help speed verification.

Finally there are three appendices at the end of the book to provide ref-

erence information. Appendix A is a listing of the IEEE 1164 STD_LOGIC

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