Xilinx SDAccel云计算开发工具全面指南（v2018.2）

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"本指南是Xilinx的云计算开发工具SDAccel的编程教程，专为Xilinx用户设计，特别是针对版本2018.2。它详细介绍了SDAccel的编译流程、执行模型，以及如何利用OpenCL环境进行编程。以下是主要内容概览： 1. SDAccel编译流程与执行模型： - SDAccel的编程模型基于硬件加速，允许开发者将部分计算任务卸载到FPGA中，以提升性能。章节详细阐述了从设计创建到实际执行的整个流程，包括定制DDR Bank与内核之间的连接，以及使用`--spoption`的语法和要求。 2. 设备拓扑与执行模型： - 设计者需要理解FPGA的硬件架构，如何组织和优化数据流，以便于高效地在不同模块间传递数据。章节中会探讨如何构建适合FPGA环境的应用执行模型。 3. 编程主机应用： - 本章指导用户设置OpenCL环境，因为SDAccel是基于OpenCL的框架。内容包括如何在主机上运行命令，以及设计完成后对FPGA的清理和后处理步骤。 4. C/C++内核编程： - 作为核心部分，这里介绍支持的数据类型、接口设计、循环控制、数据流优化技术，以及数组配置和函数内联等高级编程技巧。这些都是实现高性能加速的关键要素。 5. 示例设计： - 提供实际的设计案例，帮助读者通过实践学习和理解SDAccel的使用方法，使理论知识更具可操作性。 6. 文档组织： - 整个指南结构清晰，便于查阅，每个章节都有明确的目标和学习路径，方便读者根据需求深入学习或快速检索。本指南是Xilinx SDAccel开发人员必备的参考资料，旨在帮助开发者充分利用SDAccel工具，提高FPGA在云计算环境中的性能，并通过详尽的实例和最佳实践，提升代码效率和可移植性。"

• Each host applicaon source le is compiled to an object le (.o).

• The object les (.o) are linked with the Xilinx SDAccel runme shared library to create the

executable (.exe).

2. FPGA build process using XOCC:

• Each kernel is independently compiled to a Xilinx object (.xo) le.

○ C/C++ and OpenCL C kernels are compiled for implementaon on an FPGA using the

XOCC compiler. This step leverages the Vivado

HLS compiler. The same pragmas and

aributes supported by Vivado HLS can be used in C/C++ and OpenCL C kernel source

code to specify the desired kernel micro-architecture and control the result of the

compilaon process.

○ RTL kernels are compiled using the package_xo ulity. The RTL kernel wizard in the

SDAccel environment can be used to simplify this process.

• The kernel .xo les are linked with the hardware plaorm (.dsa) to create the FPGA

binary (.xclbin). Important architectural aspects are determined during the link step. In

parcular, this is where connecons from kernel ports to global memory banks are

established and where the number of instances for each kernel is specied.

○ When the build target is soware or hardware emulaon, as described below, xocc

generates simulaon models of the device contents.

○ When the build target is the system, or actual hardware, xocc generates the FPGA

binary for the device leveraging the Vivado

Design Suite to run synthesis and

implementaon.

Note: The xocc compiler automacally uses the Vivado HLS and Vivado Design Suite tools to build the

kernels to run on the FPGA plaorm. It uses these tools with pre-dened sengs which have proven to

provide good quality of results. Using the SDAccel environment and the xocc compiler does not require

knowledge of these tools; however, hardware savvy developers can fully leverage these tools and use all

their available features to implement kernels.

Build Targets

The SDAccel build process generates the host applicaon executable (.exe) and the FPGA

binary (.xclbin). The SDAccel build target denes the nature of FPGA binary generated by the

build process.

SDAccel provides three dierent build targets, two emulaon targets used for debug and

validaon purposes, and the default hardware target used to generate the actual FPGA binary:

• Soware Emulaon (sw_emulator): Both the host applicaon code and the kernel code are

compiled to run on the x86 processor. This allows iterave algorithm renement through fast

build and run loops. This target is useful to idenfy syntax issues, perform source-level

debugging of the kernel code running together with applicaon and verify the behavior of the

system.

Chapter 1: SDAccel Compilation Flow and Execution Model

UG1277 (v2018.2) July 2, 2018 www.xilinx.com [placeholder text]

SDAccel Environment Programmers Guide 9

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The SDAccel hardware plaorm contains global memory banks. The data transfer from the host

machine to kernels and from kernels to the host happens through these global memory banks.

The kernels running on the FPGA can have one or more memory interfaces. The connecon from

the memory banks to those memory interfaces are programmable and determined by linking

opons of the compiler.

The SDAccel execuon model follows these steps:

1. The host applicaon writes the data needed by a kernel into the global memory of the

SDAccel hardware plaorm, through the PCIe interface.

The host programs the kernel with its input parameters.

The host applicaon triggers the execuon of the kernel funcon on the FPGA.

The kernel performs the required computaon, reading and wring data from global memory

as necessary.

Kernels write data back to the memory banks, and nofy the host that it has completed its

task.

6. The host applicaon reads data back from global memory into the host memory space, and

connues processing as needed.

The FPGA can accommodate mulple kernel instances at one me; either dierent types of

kernels or mulple instances of the same kernel. The SDAccel OpenCL run me transparently

orchestrates the communicaon between the host applicaon and the kernels in the FPGAs. The

number of instances of a kernel is variable and determined by the host program and compilaon

opons.

SDAccel Emulation Flows

The SDAccel development ow can be divided into two disnct steps. The rst step is to compile

the host and kernel code to generate the executables. The second step is to run the executables

in a heterogeneous system comprised of the Host CPU and SDAccel accelerator plaorm.

However, the kernel compilaon process is long and can take several hours depending on the

size of the kernels and the architecture of the target FPGA. Therefore, to save me and shorten

the debug cycle before the kernel compilaon process, the SDAccel environment provides two

other build targets for tesng purposes: soware emulaon and hardware emulaon. The

compilaon and execuon of these emulaon targets are signicantly faster, and do not require

the actual FPGA board o be run. These emulaon ows abstract the FPGA board, and its

connecon to the host machine, into soware models to validate the combined funconality of

the host and kernel code, as well as providing some performance esmates early in the design

process. These performance esmates are just esmates, but they can greatly help debugging

and idenfying performance bolenecks. Refer to the SDAccel Environment Debugging Guide

(UG1281) for more informaon on debugging using soware and hardware emulaon ows.

Chapter 1: SDAccel Compilation Flow and Execution Model

UG1277 (v2018.2) July 2, 2018 www.xilinx.com [placeholder text]

SDAccel Environment Programmers Guide 11

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Xilinx SDAccel云计算开发工具全面指南（v2018.2）

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