SATA AHCI 1.3.1 Specification: Advanced Host Controller Interface详解

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AHCI

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AHCI 1_3_1.doc Serial ATA AHCI 1.3.1 Specification

2 HBA Configuration Registers

This section details how the PCI Header and PCI Capabilities should be constructed for an AHCI HBA.

The fields shown are duplicated from the appropriate PCI specifications. The PCI documents are the

normative specifications for these registers and this section details additional requirements for an AHCI

HBA.

Start (hex)

End (hex)

Name

PCI Header

PMCAP

PMCAP+7

PCI Power Management Capability

MSICAP

MSICAP+9

Message Signaled Interrupt Capability

2.1 PCI Header

Start (hex)

End (hex)

Symbol

Name

Identifiers

CMD

Command Register

STS

Device Status

RID

Revision ID

Class Codes

CLS

Cache Line Size

MLT

Master Latency Timer

HTYPE

Header Type

BIST

Built In Self Test (Optional)

BARS

Other Base Address Registres (Optional) <BAR0-4>

ABAR

AHCI Base Address <BAR5>

Subsystem Identifiers

EROM

Expansion ROM Base Address (Optional)

CAP

Capabilities Pointer

INTR

Interrupt Information

MGNT

Min Grant (Optional)

MLAT

Max Latency (Optional)

2.1.1 Offset 00h: ID - Identifiers

Bits

Type

Reset

Description

31:16

Impl.

Spec.

Device ID (DID): Indicates what device number assigned by the vendor.

15:00

Impl.

Spec.

Vendor ID (VID): 16-bit field which indicates the company vendor, assigned by the PCI

SIG.

2.1.2 Offset 04h: CMD - Command

Bit

Type

Reset

Description

15:11

Reserved

Interrupt Disable (ID): Disables the HBA from generating interrupts. This bit does not

have any effect on MSI operation.

RW/RO

Fast Back-to-Back Enable (FBE): When set to ‘1’, the HBA is allowed to generate fast

back-to-back cycles to different devices.

RW/RO

SERR# Enable (SEE): When set to ‘1’, the HBA is allowed to generate SERR# on any

event that is enabled for SERR# generation. When cleared to ‘0’, it is not.

Wait Cycle Enable (WCC): Reserved.

RW/RO

Parity Error Response Enable (PEE): When set to ‘1’, the HBA shall generate PERR#

when a data parity error is detected.

VGA Palette Snooping Enable (VGA): Reserved

RW/RO

Impl

Spec

Memory Write and Invalidate Enable (MWIE): When set to ‘1’, the HBA is allowed to

use the memory write and invalidate command. This feature is not necessary if the

controller does not generate this command.

Special Cycle Enable (SCE): Reserved

Serial ATA AHCI 1.3.1 Specification AHCI 1_3_1.doc

Bus Master Enable (BME): Controls the HBA’s ability to act as a master for data

transfers. When set to ‘1’, bus master activity is allowed. When cleared to ‘0’, the HBA

stops and any active DMA engines return to an idle condition. It is the equivalent of

clearing the memory space start bits (PxCMD.ST) in each port.

Memory Space Enable (MSE): Controls access to the HBA’s register memory space.

RW/

Impl

Spec

I/O Space Enable (IOSE): Controls access to the HBA’s target I/O space. If the HBA

also supports bus master IDE, this bit must be read/write. This bit should be read-only

if bus master IDE is not supported by the HBA.

2.1.3 Offset 06h: STS - Device Status

Bit

Type

Reset

Description

RWC

Detected Parity Error (DPE): Set to ‘1’ by hardware when the HBA detects a parity

error on its interface.

RWC

Signaled System Error (SSE): Set to ‘1’ by hardware when the HBA host generates

SERR#.

RWC

Received Master-Abort (RMA): Set to ‘1’ by hardware when the HBA receives a

master abort to a cycle it generated.

RWC

Received Target Abort (RTA): Set to ‘1’ by hardware when the HBA receives a target

abort to a cycle it generated.

RWC

Signaled Target-Abort (STA): Set to ‘1’ by hardware when the HBA terminates with a

target abort.

10:09

Impl.

Spec.

DEVSEL# Timing (DEVT): Controls the device select time for the HBA’s PCI interface.

Refer to the PCI specification for further details.

RWC

Master Data Pariy Error Detected (DPD): Set to ‘1’ by hardware when the HBA, as a

master, either detects a parity error or sees the parity error line asserted, and the parity

error response bit (bit 6 of the command register) is set to ‘1’.

Impl.

Spec.

Fast Back-to-Back Capable (FBC): Indicates whether the HBA can accept fast back-

to-back cycles.

Reserved

Impl.

Spec.

66 MHz Capable (C66): Indicates whether the HBA can operate at 66 MHz.

Capabilities List (CL): Indicates the presence of a capabilities list. The HBA must

support the PCI power management capability as a minimum.

Interrupt Status (IS): Indicates the interrupt status of the device (1 = asserted).

02:00

Reserved

2.1.4 Offset 08h: RID - Revision ID

Bits

Type

Reset

Description

07:00

00h

Revision ID (RID): Indicates stepping of the HBA hardware.

2.1.5 Offset 09h: CC - Class Code

Bits

Type

Reset

Description

23:16

01h

Base Class Code (BCC): Indicates that this is a mass storage device.

15:08

Impl

Spec

Sub Class Code (SCC): When set to 06h, indicates that this is a Serial ATA device.

07:00

Impl

Spec

Programming Interface (PI): When set to 01h and the Sub Class Code is set to 06h,

indicates that this is an AHCI HBA that has a major revision of 1 (as specified in the

AHCI Version register).

Informative Note: For HBAs that support RAID, the Sub Class Code reset value should be 04h and the

Programming Interface reset value should be 00h.

2.1.6 Offset 0Ch: CLS – Cache Line Size

Bits

Type

Reset

Description

07:00

00h

Cache Line Size (CLS): Indicates the cache line size for use with the memory write

and invalidate command, and as an indication on when to use the memory read

multiple, memory read line, or memory read commands.

AHCI 1_3_1.doc Serial ATA AHCI 1.3.1 Specification

2.1.7 Offset 0Dh: MLT – Master Latency Timer

Bits

Type

Reset

Description

07:00

00h

Master Latency Timer (MLT): Indicates the number of clocks the HBA is allowed to act

as a master on PCI.

2.1.8 Offset 0Eh: HTYPE – Header Type

Bits

Type

Reset

Description

Impl

Spec

Multi-Function Device (MFD): Indicates whether the HBA is part of a multi-function

device.

06:00

00h

Header Layout (HL): Indicates that the HBA uses a target device layout.

2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional)

The following register is optional, but if implemented, must look as follows.

Bits

Type

Reset

Description

BIST Capable (BC): Indicates whether the HBA has a BIST function. This does not

indicate SATA BIST capability – this is only for an HBA related BIST function.

Stat BIST (SB): Software sets this bit to ‘1’ to invoke BIST. The HBA clears this bit to

‘0’ when BIST is complete.

05:04

Reserved

03:00

Completion Code (CC): Indicates the completion code status of BIST. A non-zero

value indicates a failure.

2.1.10 Offset 10h – 20h: BARS – Other Base Addresses (Optional)

These registers allocate memory or I/O spaces for other BARs. An example application of these BARs is

to implement the native IDE and bus master IDE ranges for an HBA that wishes to support legacy

software.

2.1.11 Offset 24h: ABAR – AHCI Base Address

This register allocates space for the HBA memory registers defined in section 3. The ABAR must be

allocated to contain enough space for the global AHCI registers, the port specific registers for each port,

and any vendor specific space (if needed). It is permissible to have vendor specific space after the port

specific registers for the last HBA port.

Bit

Type

Reset

Description

31:13

Base Address (BA): Base address of register memory space. This represents a

memory space for support of 32 ports. For HBAs that support fewer than 32-ports,

more bits are allowed to be RW, and therefore less memory space is consumed. For

HBAs that have vendor specific space at the end of the port specific memory space,

more bits are allowed to be RO such that more memory space is consumed.

12:04

Reserved

Prefetchable (PF): Indicates that this range is not pre-fetchable

02:01

Type (TP): Indicates that this range can be mapped anywhere in 32-bit address space

Resource Type Indicator (RTE): Indicates a request for register memory space.

2.1.12 Offset 2Ch: SS - Sub System Identifiers

Bits

Type

Reset

Description

31:16

Impl

Spec

Subsystem ID (SSID): Indicates the sub-system identifier.

15:00

Impl

Spec

Subsystem Vendor ID (SSVID): Indicates the sub-system vendor identifier

2.1.13 Offset 30h: EROM – Expansion ROM (Optional)

Bit

Type

Reset

Description

31:00

Impl

Spec

ROM Base Address (RBA): Indicates the base address of the HBA expansion ROM.

Serial ATA AHCI 1.3.1 Specification AHCI 1_3_1.doc

2.1.14 Offset 34h: CAP – Capabilities Pointer

Bit

Type

Reset

Description

7:0

PMCAP

Capability Pointer (CP): Indicates the first capability pointer offset. It points to

the PCI Power management capability offset.

2.1.15 Offset 3Ch: INTR - Interrupt Information

Bits

Type

Reset

Description

15:08

Impl

Spec

Interrupt Pin (IPIN): This indicates the interrupt pin the HBA uses.

07:00

00h

Interrupt Line (ILINE): Software written value to indicate which interrupt line (vector)

the interrupt is connected to. No hardware action is taken on this register.

Informative Note: If the HBA is a single function PCI device, then INTR.IPIN should be set to 01h to

indicate the INTA# pin.

2.1.16 Offset 3Eh: MGNT – Minimum Grant (Optional)

Bits

Type

Reset

Description

07:00

Impl

Spec

Grant (GNT): Indicates the minimum grant time (in ¼ microseconds) that the device

wishes grant asserted.

2.1.17 Offset 3Fh: MLAT – Maximum Latency (Optional)

Bits

Type

Reset

Description

07:00

Impl

Spec

Latency (LAT): Indicates the maximum latency (in ¼ microseconds) that the device

can withstand.

2.2 PCI Power Management Capabilities

Start (hex)

End (hex)

Symbol

Name

PMCAP

PMCAP+1

PID

PCI Power Management Capability ID

PMCAP+2

PMCAP+3

PCI Power Management Capabilities

PMCAP+4

PMCAP+5

PMCS

PCI Power Management Control and Status

2.2.1 Offset PMCAP: PID - PCI Power Management Capability ID

Bit

Type

Reset

Description

15:08

Impl

Spec

Next Capability (NEXT): Indicates the location of the next capability item in the

list. This can be other capability pointers (such as Message Signaled Interrupts,

PCI-X, or PCI-Express) or it can be the last item in the list.

07:00

01h

Cap ID (CID): Indicates that this pointer is a PCI power management.

2.2.2 Offset PMCAP + 2h: PC – PCI Power Management Capabilities

Bit

Type

Reset

Description

15:11

Impl

Spec

PME_Support (PSUP): Indicates the states that can generate PME#. The encoding of

this field is as follows:

Bit

State

When set to ‘1’, PME# can be generated from D3

COLD

. When cleared

to ‘0’, PME# cannot be generated from D3

COLD

. This bit may be a ‘1’

or ‘0’ for AHCI HBAs.

When set to ‘1’, PME# can be generated from D3

HOT

. When cleared

to ‘0’, PME# cannot be generated from D3

HOT

. This bit must be ‘1’ for

AHCI HBAs.

This bit must be ‘0’ for AHCI HBAs. D2 is not a supported HBA state.

The behavior is undefined if the HBA is placed in this state.

This bit must be ‘0’ for AHCI HBAs. D1 is not a supported HBA state.

The behavior is undefined if the HBA is placed in this state.

This bit must be ‘0’ for AHCI HBAs. PME# from D0 is not supported

– interrupts are used in D0.

AHCI 1_3_1.doc Serial ATA AHCI 1.3.1 Specification

D2_Support (D2S): The D2 state is not supported for AHCI HBAs.

D1_Support (D1S): The D1 state is not supported for AHCI HBAs.

08:06

Impl

Spec

Aux_Current (AUXC): Reports the maximum Suspend well current required when in

the D3

COLD

state. Refer to the PCI specification for definition of values.

Impl

Spec

Device Specific Initialization (DSI): Indicates whether device-specific initialization is

required.

Reserved

PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#.

02:00

Impl

Spec

Version (VS): Indicates support for Revision 1.1 or higher revisions of the PCI Power

Management Specification.

2.2.3 Offset PMCAP + 4h: PMCS – PCI Power Management Control And Status

Bit

Type

Reset

Description

RWC

Impl

Spec

PME Status (PMES): Set to ‘1’ by hardware when the HBA generates PME#.

If the HBA supports waking from D3

COLD

, this bit is indeterminate at system boot. If the

HBA does not support waking from D3

COLD

, this bit is ‘0’ at system boot.

14:09

Reserved – AHCI HBA does not implement the data register.

Impl

Spec

PME Enable (PMEE): When set to ‘1’, the HBA asserts the PME# signal when PMES

is set to ‘1’.

If the HBA supports waking from D3

COLD

, this bit is indeterminate at system boot. If the

HBA does not support waking from D3

COLD

, this bit is ‘0’ at system boot.

07:02

Reserved

01:00

R/W

Power State (PS): This field is used both to determine the current power state of the

HBA and to set a new power state. The values are:

00 – D0 state

11 – D3

HOT

state

The D1 and D2 states are not supported for AHCI HBAs. When in the D3

HOT

state, the

HBA’s configuration space is available, but the register memory spaces are not.

Additionally, interrupts are blocked.

2.3 Message Signaled Interrupt Capability (Optional)

Start (hex)

End (hex)

Symbol

Name

MSICAP

MSICAP+1

MID

Message Signaled Interrupt Capability ID

MSICAP+2

MSICAP+3

Message Signaled Interrupt Message Control

MSICAP+4

MSICAP+7

Message Signaled Interrupt Message Address

MSICAP+8 (MC.C64=0)

MSICAP+C (MC.C64=1)

MSICAP+9

MSICAP.D

Message Signaled Interrupt Message Data

MSICAP+8 (MC.C64=1)

MSICAP+B

MUA

Message Signaled Interrupt Upper Address (Optional)

2.3.1 Offset MSICAP: MID – Message Signaled Interrupt Identifiers

Bits

Type

Reset

Description

15:08

Impl

Spec

Next Pointer (NEXT): Indicates the next item in the list. This can be other capability

pointers (such as PCI-X or PCI-Express) or it can be the last item in the list.

07:00

05h

Capability ID (CID): Capabilities ID indicates MSI.

2.3.2 Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control

Bits

Type

Reset

Description

15:08

Reserved

Impl

Spec

64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit

messages.

06:04

000

Multiple Message Enable (MME): Indicates the number of messages the HBA should

assert. See section 10.7.2.2. If the value programmed into this field exceeds the MMC

field in this register, the results are indeterminate.

03:01

Impl

Spec

Multiple Message Capable (MMC): Indicates the number of messages the HBA

wishes to assert. See section 10.7.2.2.

MSI Enable (MSIE): If set to ‘1’, MSI is enabled and the traditional interrupt pins are not

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