Arduino UNO 主控芯片技术手册详解

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Arduino UNO 主控芯片手册本手册旨在为 Arduino UNO 的用户提供深入的技术指导，帮助他们更好地了解和掌握该主控芯片的特性和应用。高性能、低功耗 AVR 8 位微控制器 Arduino UNO 的主控芯片基于高性能、低功耗的 AVR 8 位微控制器。该微控制器具有先进的 RISC 架构，可以在单个时钟周期内执行大多数指令。该芯片具有 32 个通用寄存器，可以实现快速的数据处理和存储。同时，该芯片还具有 Fully Static Operation 的特性，可以在低功耗模式下运行。高性能指令集该芯片的指令集具有高性能和灵活性，包括 131 个强大的指令，大多数指令可以在单个时钟周期内执行。该芯片还具有 2 个周期的乘法器，可以快速地执行乘法和除法运算。高耐用非易失存储器该芯片具有高耐用非易失存储器，包括 4/8/16/32KB 的 Flash 程序存储器、256/512/512/1KB 的 EEPROM 和 512/1K/1K/2KB 的内部 SRAM。这些存储器可以提供高可靠性和长期数据存储。高效的读写操作该芯片支持 True Read-While-Write 操作，可以在不影响程序执行的情况下进行数据读写操作。同时，该芯片还具有 Programming Lock 功能，可以保护软件的安全性。多种外围设备接口该芯片具有多种外围设备接口，包括两个 8 位定时器/计数器、一个 16 位定时器/计数器、一个实时计时器、六个 PWM 通道和一个 8 通道 10 位 ADC。这些接口可以满足不同应用场景的需求。实时计时器该芯片具有一个实时计时器，可以提供高精度的计时功能。该计时器具有独立的振荡器，可以在不同的频率下运行。 ADC 模块该芯片具有一个 8 通道 10 位 ADC 模块，可以将模拟信号转换为数字信号。该模块可以满足不同的应用场景，例如温度、湿度、照明度等的检测。 Arduino UNO 的主控芯片具有高性能、低功耗、多种外围设备接口等特性，能够满足不同的应用场景的需求。通过本手册的指导，用户可以更好地了解和掌握该芯片的特性和应用。

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega48PA/88PA/168PA/328P. The AVR

architecture has two main memory spaces, the Data Memory and the Program Memory space.

In addition, the ATmega48PA/88PA/168PA/328P features an EEPROM Memory for data stor-

age. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega48PA/88PA/168PA/328P contains 4/8/16/32K bytes On-chip In-System Repro-

grammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits

wide, the Flash is organized as 2/4/8/16K x 16. For software security, the Flash Program mem-

ory space is divided into two sections, Boot Loader Section and Application Program Section in

ATmega88PA and ATmega168PA. See SELFPRGEN description in section ”SPMCSR – Store

Program Memory Control and Status Register” on page 292 for more details.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega48PA/88PA/168PA/328P Program Counter (PC) is 11/12/13/14 bits wide, thus address-

ing the 2/4/8/16K program memory locations. The operation of Boot Program section and

associated Boot Lock bits for software protection are described in detail in ”Self-Programming

the Flash, ATmega48PA” on page 269 and ”Boot Loader Support – Read-While-Write Self-Pro-

gramming, ATmega88PA, ATmega168PA and ATmega328P” on page 277. ”Memory

Programming” on page 294 contains a detailed description on Flash Programming in SPI- or

Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 13.

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 7-4.

Figure 7-4. On-chip Data SRAM Access Cycles

7.4 EEPROM Data Memory

The ATmega48PA/88PA/168PA/328P contains 256/512/512/1K bytes of data EEPROM mem-

ory. It is organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the

EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-

ters, the EEPROM Data Register, and the EEPROM Control Register.

”Memory Programming” on page 294 contains a detailed description on EEPROM Programming

in SPI or Parallel Programming mode.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See ”Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7.4.2 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.5 I/O Memory

The I/O space definition of the ATmega48PA/88PA/168PA/328P is shown in ”Register Sum-

mary” on page 423.

All ATmega48PA/88PA/168PA/328P I/Os and peripherals are placed in the I/O space. All I/O

locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

Refer to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data

space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than

can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For

the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.5.1 General Purpose I/O Registers

The ATmega48PA/88PA/168PA/328P contains three General Purpose I/O Registers. These

registers can be used for storing any information, and they are particularly useful for storing

global variables and Status Flags. General Purpose I/O Registers within the address range 0x00

- 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

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