AR1330 13百万像素BSI CMOS图像传感器规格介绍

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AR1330是一款由Aptina Imaging Corporation生产的1/3英寸13百万像素CMOS数码图像传感器，其主要特点和规格如下： 1. **先进像素结构（BSI）**: AR1330采用了先进的1.1微米像素BSI技术，这提高了传感器的灵敏度和光捕获效率，使得在低光照条件下也能获得清晰的图像。 2. **数据接口兼容性**：该传感器支持两种和四种线程的串行移动 industry processor interface (MIPI) 数据接口，这种设计灵活性使其能够与多种处理器和系统无缝集成，满足不同应用的需求。此外，MIPI接口还提供了比特深度压缩功能，可以选择10-8和10-6的压缩级别，有助于降低数据传输带宽，同时保持全帧率的性能。 3. **立体视频捕捉能力**：AR1330内置3D同步控制功能，这使得它能够支持立体视觉应用，例如虚拟现实或增强现实设备中的3D图像捕获。 4. **自动色彩校正**：传感器内部集成了DxODPP (Direct eXtreme Optical Distortion and Pixel Pitch) 技术，能自动进行色彩阴影修正以及绿色不平衡校正，确保拍摄出来的图像色彩准确且一致性好。 5. **实时处理性能**：1300万像素的高分辨率下，AR1330提供了6K级的实时处理能力，这意味着传感器能够在短时间内完成大量的图像处理任务，提高系统响应速度。 6. **设计状态**：尽管这款产品目前处于定义阶段，但Aptina保留了对产品规格进行修改的权利，因此在购买或使用前，建议查阅最新的资料以获取最准确的产品特性。为了获取AR1330的最新规格和规格更新，用户应访问Aptina的官方网站www.aptina.com。AR1330凭借其高性能的像素技术和丰富的功能，是适合需要高质量图像采集和处理应用的理想选择，如智能手机摄像头、专业相机、无人机和工业监控等场景。

PDF: 4722220114 /Source: 1762363735 Aptina reserves the right to change products or specifications without notice.

AR1330_DS - Rev. A Pub. 6/12 EN

AR1330: 1/3-Inch 13Mp CMOS Digital Image Sensor

Signal Descriptions

Aptina Confidential and Proprietary Preview

Signal Descriptions

Table 4 provides signal descriptions for AR1330 die. For pad location and aperture infor-

mation, refer to the AR1330 die data sheet.

Table 4: Signal Descriptions

Pad Name Pad Type Description

EXTCLK Input Master clock input, 6–48 MHz.

XSHUTDOWN Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are

restored to their factory default settings. This pin will turn off the digital power domain and is the

lowest power state of the sensor.

CLK Input Serial clock for access to control and status registers.

GPI[3:2] Input General purpose inputs. After reset, these pads are powered-down by default; this means that it is not

necessary to bond to these pads. These pads can be configured to provide hardware control of:

GPI[2]: S

ADDR, Trigger signal for Slave mode and Standby

GPI[3]: 3D daisy chain communication input, all options in GPI[2]Aptina recommends that unused GPI

pins be tied to D

GND, but can also be left floating.

GPIO[1:0] Input/

Output

General purpose inputs and outputs. After reset, these pads are not powered-down since its default

use is as output. These pads can be configured to provide hardware control of:

GPIO[0]: Flash output (default), all input options in GPI[2]

GPIO[1]: Shutter output (default), 3-D daisy chain communication output and all input options in

GPI[2]

Aptina recommends that unused GPIO pins be tied to DGND, but can also be left floating.

TEST Input TEST must be tied to GND.

DATA I/O Serial data from reads and writes to control and status registers.

DATA_P Output Differential MIPI (sub-LVDS) serial data 1st lane (positive).

DATA_N Output Differential MIPI (sub-LVDS) serial data 1st lane (negative).

DATA2_P Output Differential MIPI (sub-LVDS) serial data 2nd lane (positive).

DATA2_N Output Differential MIPI (sub-LVDS) serial data 2nd lane (negative).

DATA3_P Output Differential MIPI (sub-LVDS) serial data 3rd lane (positive).

DATA3_N Output Differential MIPI (sub-LVDS) serial data 3rd lane (negative).

DATA4_P Output Differential MIPI (sub-LVDS) serial data 4th lane (positive).

DATA4_N Output Differential MIPI (sub-LVDS) serial data 4th lane (negative).

CLK_P Output Differential MIPI (sub-LVDS) serial clock/strobe (positive).

CLK_N Output Differential MIPI (sub-LVDS) serial clock/strobe (negative).

DD_PHY Supply Digital PHY power supply. Digital power supply for the serial interface (1.2V).

AA Supply Analog power supply (2.8V).

VAA_PIX Supply Analog power supply for the pixel array(2.8V).

GND Supply Analog ground.

DD Supply 1.2V digital power supply inputs.

VDD_IO Supply I/O power supply (1.8V).

GND Supply Common ground for digital and I/O.

DD_PLL Supply PLL power supply.

VCM_ISINK I/O Connected to VCM actuator. Can be left floating if not used.

VCM_GND I/O Connected to D

GND. Tie to DGND if not used.

PDF: 4722220114 /Source: 1762363735 Aptina reserves the right to change products or specifications without notice.

AR1330_DS - Rev. A Pub. 6/12 EN

AR1330: 1/3-Inch 13Mp CMOS Digital Image Sensor

Output Data Format

Aptina Confidential and Proprietary Preview

Two-Wire Serial Register Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the AR1330.The interface protocol uses a master/slave model in which a

master controls one or more slave devices. The sensor acts as a slave device. The master

generates a clock (S

CLK) that is an input to the sensor and is used to synchronize trans-

fers. Data is transferred between the master and the slave on a bidirectional signal

DATA). SDATA is pulled up to VDD off-chip by a 1.5kΩ resistor. Either the slave or master

device can drive S

DATA LOW—the interface protocol determines which device is allowed

to drive S

DATA at any given time.

The protocols described in the two-wire serial interface specification allow the slave

device to drive S

CLKLOW; the AR1330 uses SCLK as an input only and therefore never

drives it LOW.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements:

1. a (repeated) start condition

2. a slave address/data direction byte

3. an (a no) acknowledge bit

4. a message byte

5. a stop condition

The bus is idle when both S

CLK and SDATA are HIGH. Control of the bus is initiated with a

start condition, and the bus is released with a stop condition. Only the master can

generate the start and stop conditions.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each S

CLK clock period. SDATA can change when SCLK

is LOW and must be stable while S

CLK is HIGH.

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The

default slave addresses used by the AR1330 for the MIPI configured sensor are 0x6C

(write address) and 0x6D (read address) in accordance with the MIPI specification. Alter-

nate slave addresses of 0x6E(write address) and 0x6F(read address) can be selected by

enabling and asserting the S

ADDR signal through the GPI pad.

An alternate slave address can also be programmed through R0x31FC.

PDF: 4722220114 /Source: 1762363735 Aptina reserves the right to change products or specifications without notice.

AR1330_DS - Rev. A Pub. 6/12 EN

AR1330: 1/3-Inch 13Mp CMOS Digital Image Sensor

Output Data Format

Aptina Confidential and Proprietary Preview

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

CLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases S

DATA. The receiver indicates an acknowl-

edge bit by driving S

DATA LOW. As for data transfers, SDATA can change when SCLK is

LOW and must be stable while S

CLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA LOW

during the S

CLK clock period following a data transfer. A no-acknowledge bit is used to

terminate a read sequence.

Typical Sequence

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-

cates a write and a “1” indicates a read. If the address matches the address of the slave

device, the slave device acknowledges receipt of the address by generating an acknowl-

edge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

the WRITE should take place. This transfer takes place as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master then transfers the data as an 8-bit sequence; the slave sends an

acknowledge bit at the end of the sequence. The master stops writing by generating a

(re)start or stop condition.

If the request was a READ, the master sends the 8-bit write slave address/data direction

byte and 16-bit register address, the same way as with a WRITE request. The master then

generates a (re)start condition and the 8-bit read slave address/data direction byte, and

clocks out the register data, eight bits at a time. The master generates an acknowledge

bit after each 8-bit transfer. The slave’s internal register address is automatically incre-

mented after every 8 bits are transferred. The data transfer is stopped when the master

sends a no-acknowledge bit.

Single READ from Random Location

This sequence (Figure 4 on page 16) starts with a dummy WRITE to the 16-bit address

that is to be used for the READ. The master terminates the WRITE by generating a restart

condition. The master then sends the 8-bit read slave address/data direction byte and

clocks out one byte of register data. The master terminates the READ by generating a no-

acknowledge bit followed by a stop condition. Figure 4 shows how the internal register

address maintained by the AR1330 is loaded and incremented as the sequence proceeds.

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