Allwinner T3用户手册：注册块图与寄存器列表

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Contents

3.18.4.29. PD Configure Register 1(Default Value: 0x7777_7777) ............................................................ 352

3.18.4.30. PD Configure Register 2(Default Value: 0x7777_7777) ............................................................ 353

3.18.4.31. PD Configure Register 3(Default Value: 0x0000_7777) ............................................................ 355

3.18.4.32. PD Data Register(Default Value: 0x0000_0000) ....................................................................... 355

3.18.4.33. PD Multi-Driving Register 0(Default Value: 0x5555_5555) ...................................................... 356

3.18.4.34. PD Multi-Driving Register 1(Default Value: 0x0055_5555) ...................................................... 356

3.18.4.35. PD Pull Register 0(Default Value: 0x0000_0000) ..................................................................... 356

3.18.4.36. PD Pull Register 1(Default Value: 0x0000_0000) ..................................................................... 356

3.18.4.37. PE Configure Register 0(Default Value: 0x7777_7777) ............................................................ 357

3.18.4.38. PE Configure Register 1(Default Value: 0x0000_7777) ............................................................ 358

3.18.4.39. PE Configure Register 2(Default Value: 0x0000_0000) ............................................................ 359

3.18.4.40. PE Configure Register 3(Default Value: 0x0000_0000) ............................................................ 359

3.18.4.41. PE Data Register(Default Value: 0x0000_0000) ....................................................................... 359

3.18.4.42. PE Multi-Driving Register 0(Default Value: 0x0055_5555) ...................................................... 359

3.18.4.43. PE Multi-Driving Register 1(Default Value: 0x0000_0000) ....................................................... 360

3.18.4.44. PE Pull Register 0(Default Value: 0x0000_0000) ...................................................................... 360

3.18.4.45. PE Pull Register 1(Default Value: 0x0000_0000) ...................................................................... 360

3.18.4.46. PF Configure Register 0(Default Value: 0x0077_7777) ............................................................ 360

3.18.4.47. PF Configure Register 1(Default Value: 0x0000_0000) ............................................................ 361

3.18.4.48. PF Configure Register 2(Default Value: 0x0000_0000) ............................................................ 361

3.18.4.49. PF Configure Register 3(Default Value: 0x0000_0000) ............................................................ 361

3.18.4.50. PF Data Register(Default Value: 0x0000_0000) ....................................................................... 362

3.18.4.51. PF Multi-Driving Register 0(Default Value: 0x0000_0555) ....................................................... 362

3.18.4.52. PF Multi-Driving Register 1(Default Value: 0x0000_0000) ....................................................... 362

3.18.4.53. PF Pull Register 0(Default Value: 0x0000_0000) ...................................................................... 362

3.18.4.54. PF Pull Register 1(Default Value: 0x0000_0000) ...................................................................... 362

3.18.4.55. PG Configure Register 0(Default Value: 0x7777_7777)............................................................ 363

3.18.4.56. PG Configure Register 1(Default Value: 0x0000_7777) ............................................................ 364

3.18.4.57. PG Configure Register 2(Default Value: 0x0000_0000) ............................................................ 365

3.18.4.58. PG Configure Register 3(Default Value: 0x0000_0000) ............................................................ 365

3.18.4.59. PG Data Register(Default Value: 0x0000_0000) ....................................................................... 365

3.18.4.60. PG Multi-Driving Register 0(Default Value: 0x0055_5555) ...................................................... 365

3.18.4.61. PG Multi-Driving Register 1(Default Value: 0x0000_0000) ...................................................... 365

3.18.4.62. PG Pull Register 0(Default Value: 0x0000_0000) ..................................................................... 366

3.18.4.63. PG Pull Register 1(Default Value: 0x0000_0000) ..................................................................... 366

3.18.4.64. PH Configure Register 0(Default Value: 0x3333_3333) ............................................................ 366

3.18.4.65. PH Configure Register 1(Default Value: 0x0033_0000) ............................................................ 367

3.18.4.66. PH Configure Register 2(Default Value: 0x6655_0005) ............................................................ 369

3.18.4.67. PH Configure Register 3(Default Value: 0x0000_6666) ............................................................ 370

3.18.4.68. PH Data Register(Default Value: 0x0000_0000) ....................................................................... 370

3.18.4.69. PH Multi-Driving Register 0(Default Value: 0x5555_5555) ...................................................... 371

3.18.4.70. PH Multi-Driving Register 1(Default Value: 0x0055_5555) ...................................................... 371

3.18.4.71. PH Pull Register 0(Default Value: 0x0000_0000) ..................................................................... 371

3.18.4.72. PH Pull Register 1(Default Value: 0x0000_0000)...................................................................... 371

3.18.4.73. PI Configure Register 0(Default Value: 0x7777_7777) ............................................................. 372

3.18.4.74. PI Configure Register 1(Default Value: 0x7777_7777) ............................................................. 373

3.18.4.75. PI Configure Register 2(Default Value: 0x0077_7777) ............................................................. 374

3.18.4.76. PI Configure Register 3(Default Value: 0x0000_0000) ............................................................. 375

3.18.4.77. PI Data Register(Default Value: 0x0000_0000) ........................................................................ 375

3.18.4.78. PI Multi-Driving Register 0(Default Value: 0x5555_5555) ....................................................... 376

3.18.4.79. PI Multi-Driving Register 1(Default Value: 0x0000_0555) ....................................................... 376

3.18.4.80. PI Pull Register 0(Default Value: 0x0000_0000) ....................................................................... 376

3.18.4.81. PI Pull Register 1(Default Value: 0x0000_0000) ....................................................................... 376

3.18.4.82. PIO Interrupt Configure Register 0(Default Value: 0x0000_0000) ........................................... 377

Contents

3.18.4.83. PIO Interrupt Configure Register 1(Default Value: 0x0000_0000) ........................................... 377

3.18.4.84. PIO Interrupt Configure Register 2(Default Value: 0x0000_0000) ........................................... 377

3.18.4.85. PIO Interrupt Configure Register 3(Default Value: 0x0000_0000) ........................................... 378

3.18.4.86. PIO Interrupt Control Register(Default Value: 0x0000_0000) .................................................. 378

3.18.4.87. PIO Interrupt Status Register(Default Value: 0x0000_0000) .................................................... 378

3.18.4.88. PIO Interrupt Debounce Register(Default Value: 0x0000_0000) ............................................. 378

Chapter 4. Memory ........................................................................................................................................................... 379

4.1. DRAMC ............................................................................................................................................................... 380

4.1.1. Overview ................................................................................................................................................. 380

4.2. NAND Flash Controller(NDFC) ............................................................................................................................ 381

4.2.1. Overview ................................................................................................................................................. 381

4.2.2. Block Diagram ......................................................................................................................................... 381

4.2.3. Operations and Functional Descriptions ................................................................................................. 382

4.2.3.1. External Signals ............................................................................................................................ 382

4.2.3.2. Clock Sources................................................................................................................................ 383

4.2.3.3. NDFC Timing Diagram .................................................................................................................. 383

4.2.3.4. NDFC Operation Guide ................................................................................................................. 388

4.2.4. Register List ............................................................................................................................................. 389

4.2.5. Register Description ................................................................................................................................ 390

4.2.5.1. NDFC Control Register(Default Value: 0x0000_0000) .................................................................. 390

4.2.5.2. NDFC Status Register(Default Value: 0x0000_0000) .................................................................... 392

4.2.5.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x0000_0000) ................................... 393

4.2.5.4. NDFC Timing Control Register(Default Value: 0x0000_0000) ...................................................... 393

4.2.5.5. NDFC Timing Configure Register(Default Value: 0x0000_0095) .................................................. 394

4.2.5.6. NDFC Address Low Word Register(Default Value: 0x0000_0000) ................................................ 395

4.2.5.7. NDFC Address High Word Register(Default Value: 0x0000_0000) ............................................... 396

4.2.5.8. NDFC Data Block Number Register(Default Value: 0x0000_0000) .............................................. 396

4.2.5.9. NDFC Data Counter Register(Default Value: 0x0000_0000) ........................................................ 396

4.2.5.10. NDFC Command IO Register(Default Value: 0x0000_0000) ...................................................... 396

4.2.5.11. NDFC Command Set Register 0(Default Value: 0x00E0_0530) .................................................. 398

4.2.5.12. NDFC Command Set Register 1(Default Value: 0x7000_8510) .................................................. 398

4.2.5.13. NDFC ECC Control Register(Default Value: 0x4A80_0008) ........................................................ 399

4.2.5.14. NDFC ECC Status Register(Default Value: 0x0000_0000) ........................................................... 400

4.2.5.15. NDFC Enhanced Feature Register(Default Value: 0x0000_0000) ............................................... 400

4.2.5.16. NDFC Error Counter Register 0(Default Value: 0x0000_0000) ................................................... 400

4.2.5.17. NDFC Error Counter Register 1(Default Value: 0x0000_0000) ................................................... 401

4.2.5.18. NDFC Error Counter Register 2(Default Value: 0x00000000) ..................................................... 401

4.2.5.19. NDFC Error Counter Register 3(Default Value: 0x0000_0000) ................................................... 401

4.2.5.20. NDFC User Data Register [n]( Default Value:0xFFFF_FFFF) ........................................................ 402

4.2.5.21. NDFC EFNAND Status Register(Default Value: 0x0000_0000) ................................................... 402

4.2.5.22. NDFC Spare Area Register(Default Value: 0x0000_0400) .......................................................... 402

4.2.5.23. NDFC Pattern ID Register(Default Value: 0x0000_0000) ........................................................... 402

4.2.5.24. NDFC Read Data Status Control Register(Default Value: 0x0100_0000) ................................... 403

4.2.5.25. NDFC Read Data Status Register 0(Default Value: 0x0000_0000) ............................................. 403

4.2.5.26. NDFC Read Data Status Register 1(Default Value: 0x0000_0000) ............................................. 403

4.2.5.27. NDFC MBUS DMA Address Register(Default Value: 0x0000_0000) ........................................... 403

4.2.5.28. NDFC MBUS DMA Byte Counter Register(Default Value: 0x0000_0000) ................................... 404

4.2.5.29. NDFC Normal DMA Mode Control Register(Default Value: 0x0000_00A5) ............................... 404

4.2.5.30. NDFC IO Data Register(Default Value: 0x0000_0000) ................................................................ 404

4.3. SD-MMC Host Controller(SMHC) ....................................................................................................................... 405

4.3.1. Overview ................................................................................................................................................. 405

4.3.2. Block Diagram ......................................................................................................................................... 405

4.3.3. Operations and Functional Descriptions ................................................................................................. 406

4.3.3.1. External Signals ............................................................................................................................ 406

Contents

4.3.3.2. Clock Sources................................................................................................................................ 406

4.3.3.3. Timing Diagram ............................................................................................................................ 406

4.3.3.4. Calibrate Delay Chain ................................................................................................................... 407

4.3.3.5. SMHC DMA Controller Description .............................................................................................. 407

4.3.4. Register List ............................................................................................................................................. 409

4.3.5. Register Description ................................................................................................................................ 410

4.3.5.1. SMHC Global Control Register(Default Value: 0x0000_0100) ...................................................... 410

4.3.5.2. SMHC Clock Control Register(Default Value: 0x0000_0000) ........................................................ 411

4.3.5.3. SMHC Timeout Register(Default Value: 0xFFFF_FF40) ................................................................ 412

4.3.5.4. SMHC Bus Width Register(Default Value: 0x0000_0000) ............................................................ 412

4.3.5.5. SMHC Block Size Register(Default Value: 0x0000_0200) ............................................................. 412

4.3.5.6. SMHC Byte Count Register(Default Value: 0x0000_0200) ........................................................... 412

4.3.5.7. SMHC Command Register(Default Value: 0x0000_0000) ............................................................ 412

4.3.5.8. SMHC Command Argument Register(Default Value: 0x0000_0000) ........................................... 414

4.3.5.9. SMHC Response 0 Register(Default Value: 0x0000_0000) ........................................................... 414

4.3.5.10. SMHC Response 1 Register(Default Value: 0x0000_0000) ......................................................... 415

4.3.5.11. SMHC Response 2 Register(Default Value: 0x0000_0000) ......................................................... 415

4.3.5.12. SMHC Response 3 Register(Default Value: 0x0000_0000) ......................................................... 415

4.3.5.13. SMHC Interrupt Mask Register(Default Value: 0x0000_0000) ................................................... 415

4.3.5.14. SMHC Masked Interrupt Status Register(Default Value: 0x0000_0000) .................................... 416

4.3.5.15. SMHC Raw Interrupt Status Register(Default Value: 0x0000_0000) .......................................... 417

4.3.5.16. SMHC Status Register(Default Value: 0x0000_0006) ................................................................. 419

4.3.5.17. SMHC FIFO Water Level Register(Default Value: 0x000F_0000) ................................................ 420

4.3.5.18. SMHC Function Select Register(Default Value: 0x0000_0000) .................................................. 421

4.3.5.19. SMHC Transferred Byte Count Register0(Default Value: 0x0000_0000) .................................... 422

4.3.5.20. SMHC Transferred Byte Count Register1(Default Value: 0x0000_0000) .................................... 422

4.3.5.21. SMHC Auto Command 12 Argument Register(Default Value: 0x0000_FFFF)............................. 422

4.3.5.22. SMHC New Timing Set Register(Default Value: 0x8171_0000) .................................................. 422

4.3.5.23. SMHC Hardware Reset Register(Default Value: 0x0000_0001) ................................................. 424

4.3.5.24. SMHC DMAC Control Register(Default Value: 0x0000_0000) .................................................... 424

4.3.5.25. SMHC Descriptor List Base Address Register(Default Value: 0x0000_0000) .............................. 425

4.3.5.26. SMHC DMAC Status Register(Default Value: 0x0000_0000) ...................................................... 425

4.3.5.27. SMHC DMAC Interrupt Enable Register(Default Value: 0x0000_0000) ...................................... 426

4.3.5.28. SMHC Current Host Descriptor Address Register(Default Value: 0x0000_0000) ....................... 427

4.3.5.29. SMHC Current Buffer Descriptor Address Register(Default Value: 0x0000_0000) ..................... 428

4.3.5.30. SMHC Card Threshold Control Register(Default Value: 0x0000_0000) ...................................... 428

4.3.5.31. SMHC eMMC4.5 DDR Start Bit Detection Control Register(Default Value: 0x0000_0000) ........ 428

4.3.5.32. SMHC Response CRC Register(Default Value: 0x0000_0000) .................................................... 429

4.3.5.33. SMHC Data7 CRC Register(Default Value: 0x0000_0000) .......................................................... 429

4.3.5.34. SMHC Data6 CRC Register(Default Value: 0x0000_0000) .......................................................... 429

4.3.5.35. SMHC Data5 CRC Register(Default Value: 0x0000_0000) .......................................................... 430

4.3.5.36. SMHC Data4 CRC Register(Default Value: 0x0000_0000) .......................................................... 430

4.3.5.37. SMHC Data3 CRC Register(Default Value: 0x0000_0000) .......................................................... 430

4.3.5.38. SMHC Data2 CRC Register(Default Value: 0x0000_0000) .......................................................... 431

4.3.5.39. SMHC Data1 CRC Register(Default Value: 0x0000_0000) .......................................................... 431

4.3.5.40. SMHC Data0 CRC Register(Default Value: 0x0000_0000) .......................................................... 431

4.3.5.41. SMHC CRC Status Register(Default Value: 0x0000_0000) .......................................................... 432

4.3.5.42. SMHC Drive Delay Control Register(Default Value: 0x0001_0000) ............................................ 432

4.3.5.43. SMHC Sample Delay Control Register(Default Value: 0x0000_2000) ........................................ 432

4.3.5.44. SMHC Data Strobe Delay Control Register(Default Value: 0x0000_2000) ................................. 433

4.3.5.45. SMHC FIFO Register(Default Value: 0x0000_0000) .................................................................... 433

Chapter 5. Graphic ............................................................................................................................................................ 434

5.1. Mixer Processor ................................................................................................................................................. 435

5.1.1. Overview ................................................................................................................................................. 435

Contents

5.1.2. Block Diagram ......................................................................................................................................... 436

5.1.3. Clock Sources .......................................................................................................................................... 436

5.1.4. Register List ............................................................................................................................................. 436

5.1.5. Register Description ................................................................................................................................ 438

5.1.5.1. Mixer Control Register(Default Value: 0x0000_0000) .................................................................. 438

5.1.5.2. Mixer Status Register(Default Value: 0x0000_0000) .................................................................... 439

5.1.5.3. Mixer Input DMA Scan Order Register(Default Value: 0x0000_0000) ......................................... 439

5.1.5.4. Mixer Input DMA High 4bit Address Register(Default Value: 0x0000_0000) ............................... 439

5.1.5.5. Mixer Input DMA Low 32bit Address Register(Default Value: 0x0000_0000) ............................. 440

5.1.5.6. Mixer Input DMA Pitch Register(Default Value: 0x0000_0000) ................................................... 440

5.1.5.7. Mixer Input DMA Memory Block Size Register(Default Value: 0x0000_0000)............................. 440

5.1.5.8. Mixer Input DMA Memory Block Coordinate Register(Default Value: 0x0000_0000) ................. 440

5.1.5.9. Mixer Input DMA Setting Register(Default Value: 0x0000_0000) ................................................ 441

5.1.5.10. Mixer Input DMA Fill-color Register(Default Value: 0x0000_0000) ........................................... 442

5.1.5.11. Mixer Color Space Converter 0 Register(Default Value: 0x0000_0000) ..................................... 442

5.1.5.12. Mixer Color Space Converter 1 Register(Default Value: 0x0000_0000) ..................................... 443

5.1.5.13. Mixer Scaling Control Register(Default Value: 0x0000_0000) .................................................... 443

5.1.5.14. Mixer Scaling Output Size Register(Default Value: 0x0000_0000) ............................................. 444

5.1.5.15. Mixer Scaling Horizontal Factor Register(Default Value: 0x0000_0000) .................................... 444

5.1.5.16. Mixer Scaling Vertical Factor Register(Default Value: 0x0000_0000) ........................................ 444

5.1.5.17. Mixer Scaling Horizontal Start Phase Register(Default Value: 0x0000_0000) ............................ 445

5.1.5.18. Mixer Scaling Vertical Start Phase Register(Default Value: 0x0000_0000) ................................ 445

5.1.5.19. Mixer ROP Control Register(Default Value: 0x0000_0000) ........................................................ 445

5.1.5.20. Mixer ROP Channel 3 Index 0 Setting Register(Default Value: 0x0000_0000) ........................... 447

5.1.5.21. Mixer ROP Channel 3 Index 1 Setting Register(Default Value: 0x0000_0000) ........................... 448

5.1.5.22. Mixer Alpha Color Key Control Register(Default Value: 0x0000_0000) ..................................... 449

5.1.5.23. Mixer Color key Min Color Register(Default Value: 0x0000_0000) ............................................ 450

5.1.5.24. Mixer Color key Max Color Register(Default Value: 0x0000_0000) ........................................... 451

5.1.5.25. Mixer Color Space Converter 2 Control Register(Default Value: 0x0000_0000) ........................ 451

5.1.5.26. Mixer Output Control Register(Default Value: 0x0000_0000) ................................................... 451

5.1.5.27. Mixer Output Size Register(Default Value: 0x0000_0000) ......................................................... 452

5.1.5.28. Mixer Output High 4bit Address Register(Default Value: 0x0000_0000) ................................... 453

5.1.5.29. Mixer Output Low 32bit Address Register(Default Value: 0x0000_0000) .................................. 453

5.1.5.30. Mixer Output Pitch Register(Default Value: 0x0000_0000) ....................................................... 453

5.1.5.31. Mixer Output Alpha Control Register(Default Value: 0x0000_0000) ......................................... 453

5.1.5.32. Mixer CSC0/1 Y/G Coefficient0 Register(Default Value: 0x04A7_04A7) ..................................... 454

5.1.5.33. Mixer CSC0/1 Y/G Coefficient1 Register(Default Value: 0x1E6F_1E6F) ...................................... 455

5.1.5.34. Mixer CSC0/1 Y/G Coefficient2 Register(Default Value: 0x1CBF_1CBF) ..................................... 455

5.1.5.35. Mixer CSC0/1 Y/G Constant Register(Default Value: 0x0877_0877) .......................................... 455

5.1.5.36. Mixer CSC0/1 U/R Coefficient0 Register(Default Value: 0x04A7_04A7) .................................... 455

5.1.5.37. Mixer CSC0/1 U/R Coefficient1 Register(Default Value: 0x0000_0000) ..................................... 456

5.1.5.38. Mixer CSC0/1 U/R Coefficient2 Register(Default Value: 0x0662_0662) ..................................... 456

5.1.5.39. Mixer CSC0/1 U/R Constant Register(Default Value: 0x3211_3211) .......................................... 456

5.1.5.40. Mixer CSC0/1 V/B Coefficient0 Register(Default Value: 0x04A7_04A7) ..................................... 456

5.1.5.41. Mixer CSC0/1 V/B Coefficient1 Register(Default Value: 0x0812_0812) ..................................... 457

5.1.5.42. Mixer CSC0/1 V/B Coefficient2 Register(Default Value: 0x0000_0000) ..................................... 457

5.1.5.43. Mixer CSC0/1 V/B Constant Register(Default Value: 0x0000_0000) .......................................... 457

5.1.5.44. Mixer CSC2 Y/G Coefficient Register(Default Value: 0x0000_0000)........................................... 458

5.1.5.45. Mixer CSC2 Y/G Constant Register(Default Value: 0x0000_0000) .............................................. 458

5.1.5.46. CSC2 U/R Coefficient Register(Default Value: 0x0000_0000) .................................................... 458

5.1.5.47. Mixer CSC2 U/R Constant Register(Default Value: 0x0000_0000) ............................................. 458

5.1.5.48. Mixer CSC2 V/B Coefficient Register(Default Value: 0x0000_0000)........................................... 458

5.1.5.49. Mixer CSC2 V/B Constant Register(Default Value: 0x0000_0000) .............................................. 459

5.1.5.50. Mixer Scaling Horizontal Filtering Coefficient RAM Register(Default Value: 0x0000_0000)...... 459

Contents

5.1.5.51. Mixer Scaling Vertical Filtering Coefficient RAM Register(Default Value: 0x0000_0000) .......... 459

5.1.5.52. Mixer Palette Table RAM ............................................................................................................ 459

Chapter 6. Image ............................................................................................................................................................... 460

6.1. CSI....................................................................................................................................................................... 461

6.1.1. Overview ................................................................................................................................................. 461

6.1.2. Block Diagram ......................................................................................................................................... 461

6.1.3. Operations and Functional Descriptions ................................................................................................. 462

6.1.3.1. External Signals ............................................................................................................................ 462

6.1.3.2. Clock Sources ............................................................................................................................... 463

6.1.3.3. CSI FIFO Distribution .................................................................................................................... 463

6.1.3.4. CCIR656 Head Code ...................................................................................................................... 464

6.1.4. Register List ............................................................................................................................................. 465

6.1.5. Register Description ................................................................................................................................ 467

6.1.5.1. CSI0 Enable Register(Default Value: 0x0000_0000) ..................................................................... 467

6.1.5.2. CSI0 Configuration Register(Default Value: 0x0030_0205) .......................................................... 468

6.1.5.3. CSI0 Capture Control Register(Default Value: 0x0000_0000) ...................................................... 470

6.1.5.4. CSI0 Horizontal Scale Register(Default Value: 0x0F00_FFFF) ....................................................... 470

6.1.5.5. CSI0 Channel_0~3 FIFO 0 Output Buffer-A Address Register(Default Value: 0x0000_0000) ....... 470

6.1.5.6. CSI0 Channel_0~3 FIFO 0 Output Buffer-B Address Register(Default Value: 0x0000_0000) ....... 470

6.1.5.7. CSI0 Channel_0~3 FIFO 1 Output Buffer-A Address Register(Default Value: 0x0000_0000) ....... 471

6.1.5.8. CSI0 Channel_0~3 FIFO 1 Output Buffer-B Address Register(Default Value: 0x0000_0000) ....... 471

6.1.5.9. CSI0 Channel_0~3 FIFO 2 Output Buffer-A Address Register(Default Value: 0x0000_0000) ....... 471

6.1.5.10. CSI0 Channel_0~3 FIFO 2 Output Buffer-B Address Register(Default Value: 0x0000_0000) ..... 471

6.1.5.11. CSI0 Channel_0~3 Output Buffer Control Register(Default Value: 0x0000_0000) ..................... 471

6.1.5.12. CSI0 Channel_0~3 Status Register(Default Value: 0x0000_0000) .............................................. 472

6.1.5.13. CSI0 Channel_0~3 Interrupt Enable Register(Default Value: 0x0000_0000) ............................. 472

6.1.5.14. CSI0 Channel_0~3 Interrupt Status Register(Default Value: 0x0000_0000) .............................. 473

6.1.5.15. CSI0 Channel_0~3 Horizontal Size Register(Default Value: 0x0500_0000) ................................ 474

6.1.5.16. CSI0 Channel_0~3 Vertical Size Register(Default Value: 0x01E0_0000) ..................................... 474

6.1.5.17. CSI0 Channel_0~3 Buffer Length Register(Default Value: 0x0000_0280) .................................. 474

6.1.5.18. CSI1 Enable Register(Default Value: 0x0000_0000) ................................................................... 474

6.1.5.19. CSI1 Configuration Register(Default Value: 0x0030_0205) ........................................................ 475

6.1.5.20. CSI1 Capture Control Register(Default Value: 0x0000_0000) .................................................... 477

6.1.5.21. CSI1 Horizontal Scale Register(Default Value: 0x0F00_FFFF) ..................................................... 477

6.1.5.22. CSI1 Channel_0 FIFO 0 Output Buffer-A Address Register(Default Value:0x0000_0000) .......... 477

6.1.5.23. CSI1 Channel_0 FIFO 0 Output Buffer-B Address Register(Default Value:0x0000_0000) .......... 478

6.1.5.24. CSI1 Channel_0 FIFO 1 Output Buffer-A Address Register(Default Value:0x0000_0000) .......... 478

6.1.5.25. CSI1 Channel_0 FIFO 1 Output Buffer-B Address Register(Default Value:0x0000_0000) .......... 478

6.1.5.26. CSI1 Channel_0 FIFO 2 Output Buffer-A Address Register(Default Value:0x0000_0000) .......... 478

6.1.5.27. CSI1 Channel_0 FIFO 2 Output Buffer-B Address Register(Default Value:0x0000_0000)........... 478

6.1.5.28. CSI1 Channel_0 Output Buffer Control Register(Default Value:0x0000_0000) .......................... 479

6.1.5.29. CSI1 Channel_0 Status Register(Default Value:0x0000_0000) ................................................... 479

6.1.5.30. CSI1 Channel_0 Interrupt Enable Register(Default Value: 0x0000_0000) ................................. 480

6.1.5.31. CSI1 Channel_0 Interrupt Status Register(Default Value: 0x0000_0000) .................................. 480

6.1.5.32. CSI1 Channel_0 Horizontal Size Register(Default Value: 0x0500_0000) .................................... 481

6.1.5.33. CSI Channel_0 Vertical Size Register(Default Value: 0x01E0_0000) ........................................... 481

6.1.5.34. CSI Channel_0 Buffer Length Register ........................................................................................ 481

6.2. TV Decoder ......................................................................................................................................................... 482

6.2.1. Overview ................................................................................................................................................. 482

6.2.2. Block Diagram ......................................................................................................................................... 482

6.2.3. Operations and Functional Descriptions ................................................................................................. 483

6.2.3.1. External Signals ............................................................................................................................ 483

6.2.3.2. Clock Sources................................................................................................................................ 483

6.2.3.3. Timing Diagram ............................................................................................................................ 483