Verilog HDL逻辑综合入门

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"Introduction to Logic Synthesis using Verilog HDL" 是一本由Robert B. Reese和Mitchell A. Thornton合著的专业书籍，由Morgan & Claypool出版社出版。该书主要探讨了使用Verilog HDL进行逻辑综合的基础知识和技术。 Verilog HDL是一种硬件描述语言（HDL），被广泛用于数字电子系统的建模、设计和验证。逻辑综合是将高级的、行为级的Verilog代码转换为低级的、门级网络列表的过程，这个过程是芯片设计流程中的关键步骤。通过逻辑综合，设计师可以将抽象的设计概念转化为实际的电路实现，以满足性能、面积和功耗的目标。本书首先会介绍Verilog的基本语法和概念，包括数据类型、运算符、结构体、模块等，这些都是进行逻辑设计的基础。然后，它会深入到逻辑综合的基本原理，如布尔代数和简化，以及如何使用这些理论来优化逻辑设计。此外，书中可能还会讨论到时序分析、约束处理、面积与速度权衡、并行和串行化设计等关键主题。在实际应用部分，读者可能会学习到如何使用综合工具，如Synopsys的Design Compiler或Aldec的Active-HDL，进行设计输入、约束设定、综合运行和后综合分析。书中可能还包含了一些案例研究和练习题，以帮助读者理解和实践逻辑综合技术。逻辑综合的一个重要方面是优化，包括逻辑等效替换、门级延迟的减少和资源的复用等。作者可能会讲解如何通过综合工具进行这些优化，以达到更好的电路性能。此外，对于现代SoC（系统级芯片）设计，IP重用和接口标准化也是重要的话题，书中可能也会涉及。 “Introduction to Logic Synthesis using Verilog HDL”为读者提供了一个全面了解和掌握Verilog HDL逻辑综合的平台，无论是对于学术研究还是工业界的实际工程设计，都是宝贵的参考资料。通过阅读这本书，读者将能够理解逻辑综合的基本流程，学会使用Verilog进行有效的数字系统设计，并具备解决实际设计问题的能力。

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P1: IML/FFX P2: IML

MOBK046-01 MOBK046-Thornton.cls October 14, 2006 13:14

6 INTRODUCTION TO LOGIC SYNTHESIS USING VERILOG HDL

FIGURE 1.5: One-bit 2-to-1 multiplexer implementations using assign statements

written, so the interface of the three modules remains the same. These examples have the input

signals ﬁrst, followed by the output signal, but the order is arbitrary. The

input and output

statements that follow the module declaration deﬁne the direction of each interface signal. A

port is declared bidirectional by using the

inout keyword. These examples list all of the input

ports using a single

input statement; individual input statements could have also been used.

Our examples use lowercase for user-deﬁned names such as module and port names; uppercase

is commonly used as well. It is suggested that mixed case not be used for user-deﬁned names,

as the tools that operate on the design data after they have been transformed from Verilog to

some intermediate format may have difﬁculty with mixed-case names.

assign statement makes a continuous assignment of the right-side expression to the

net or port that appears on the left side, using the “=” operator. The best way to think of a

continuous assignment is that the right-side expression deﬁnes a block of combinational logic,

whose output is continuously connected, and thus continuously drives, the net or the port on the

left side. Fig. 1.5(a) uses a single

assign statement to specify a 2-to-1 multiplexer using Boolean

operators. Fig. 1.5(b) divides the Boolean operators across multiple

assign statements, using

internal nets (gate ports joined by a wire)

na and nb in the last assign statement to implement

the ﬁnal or gate. The

wire statement is used to declare nets na and nb; this is not strictly

necessary as only multibit nets (busses) have to be explicitly declared. Fig. 1.5(c) uses the

conditional operator “?” in a single assignment to specify the multiplexer logic. The ﬁrst operand

in the conditional operator is the select operand (i.e.,

s); if this operand evaluates as nonzero then

the second operand (i.e.,

a) is evaluated and returned, else the third operand is evaluated and

returned. A module is terminated using the

endmodule keyword. All of these implementations

result in the same logic; none of them have any inherent advantages over the others.

P1: IML/FFX P2: IML

MOBK046-01 MOBK046-Thornton.cls October 14, 2006 13:14

DIGITAL LOGIC REVIEW WITH VERILOG QUICKSTART 9

of an always block can be one or more statements; begin and end keywords are used to

group multiple statements. The statement “

reg y;

” is included in each of the three modules

of Fig. 1.8 as any net that is assigned within an

always block must be declared as a reg type;

this does not imply that this net is driven by a register or sequential logic.

Fig. 1.8(a) implements the multiplexer using an

if-else statement, with the if-body

evaluated for a nonzero (true) conditional expression and the

else clause evaluated otherwise.

Keywords

begin

and end can be used to place multiple statements in an if-body or else clause.

Fig. 1.8(b) implements the multiplexer using Boolean operators, while Fig. 1.8(c) distributes

the Boolean operators using intermediate nets and multiple assignments. The “=” operator

when used in an

always block is called a blocking assignment, this terminology is discussed in

more detail in Section 1.6, which covers event-driven simulation principles. The

always block

of Fig. 1.8(c) uses an implicit event list designated by “

∗

,” which means that all nets on the

right side of the assignments are included in the event list.

The semantics of the net assignments in an

always blocks differs signiﬁcantly from

assign

statements in that statements in an

always

block use the same sequential execution

model as the statements in an HLL.

•

The logic synthesized for an

always block duplicates the assignments’ behavior as-

suming that the assignments are evaluated sequentially. This means that the order in

which assignments are written in an

always blocks affects the logic that is synthesized.

•

Because of the sequential nature of an

always block, the same net can be assigned

multiple times in an

always block; the last assignment takes precedence.

Fig. 1.9 shows a case in which multiple blocking assignments are made to a net in the same

always block, with assignment ordering affecting the synthesized logic. In Fig. 1.9(a), the

clr input takes precedence over the ld input if both are “1,” while in Fig. 1.9(b) the opposite

holds true. Observe that in the two

always blocks, if both ld and clr are “0,” then the initial

assignment of

q=q old sets the value of q. This is a common coding style used in combinational

logic

always blocks in that a default assignment is made to an output at the block’s beginning,

which is then overridden by later assignments in the block based upon the assertion of other

inputs.

The use of a default assignment to the output net of a combinational

always block

guarantees that the output net is the target of an assignment for any input combination. If there

is some logic path through the

always block that does not assign a value to the output net, then

a latch is inferred on that output as shown in Fig. 1.10. A latch is a sequential logic element,

and should not be synthesized in an

always block that is meant to implement combinational

logic. Inferred latches are a common coding mistake for users who are new to Verilog and logic

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