三星Flash存储器K9系列在DSP与单片机开发中的应用

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"这篇文档主要涉及的是存储器技术，特别是FLASH MEMORY的相关型号，如K9F4G08U0A和K9K8G08U1A，这些都是三星电子推出的NAND Flash内存产品。文档可能是产品规格的初步介绍，强调了三星有权在不通知的情况下更改产品或规格。此外，文档还提到了使用这些产品的注意事项，警告它们不适用于生命支持、医疗、安全设备等关键应用，以免因产品故障导致人身伤害。" 本文档详细介绍了用于DSP（数字信号处理器）和单片机开发中的存储器，特别是FLASH MEMORY的部分。FLASH MEMORY是一种非易失性存储技术，数据在断电后仍能保持，常用于嵌入式系统和各种电子设备的存储需求。 K9F4G08U0A和K9K8G08U1A是三星电子生产的两种不同型号的NAND Flash内存。这些型号可能有不同的存储容量和性能参数，例如K9F4G08U0A可能是512Mx8位的配置，而K9K8G08U1A可能是1Gx8位的配置，分别代表了存储单元的数量和每个单元的数据宽度。NAND Flash因其高密度和低成本，常用于存储大量数据，如操作系统、应用程序和用户文件。文档中提到的“Preliminary”可能意味着这些数据表是初步版本，意味着规格和特性可能会随着产品开发的进展而发生变化。因此，开发者在设计系统时应关注最新的产品规格，以确保兼容性和可靠性。文档的修订历史部分暗示了该文档可能经过多次更新，提供了关于产品信息的动态变化，对于跟踪产品发展和改进至关重要。此外，三星明确指出其产品不适用于生命支持、关键护理、医疗、安全设备等对产品可靠性要求极高的领域，因为这些设备的故障可能导致生命损失或人身伤害。这也提示了在选择和使用存储器时，必须充分考虑应用环境的安全性要求。这篇文档为DSP和单片机的开发人员提供了关于三星NAND Flash内存的详细信息，包括产品型号、潜在的变化以及使用限制，有助于他们在设计过程中做出合适的选择。同时，它也提醒了开发者在使用这类产品时应考虑的风险和责任。

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

2K Bytes 64 Bytes

Figure 1. K9F4G08U0A Functional Block Diagram

Figure 2. K9F4G08U0A Array Organization

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A8 A9 A10 A11 *L *L *L *L

3rd Cycle A

12 A13 A14 A15 A16 A17 A18 A19

4th Cycle A20 A21 A22 A23 A24 A25 A26 A27

5th Cycle A28 A29 *L *L *L *L *L *L

VCC

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

A12 - A29

A0 - A11

Command

CLE

I/0 0

I/0 7

VCC

VSS

256K Pages

(=4,096 Blocks)

2K Bytes

8 bit

64 Bytes

1 Block = 64 Pages

(128K + 4k) Byte

I/O 0 ~ I/O 7

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)B x 64 Pages

= (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 4,096 Blocks

= 4,224 Mbits

Row Address

Page Register

ALE

4,096M + 128M Bit

NAND Flash

ARRAY

(2,048 + 64)Byte x 262,144

Y-Gating

Row Address

Column Address

Row Address

Data Register & S/A

FLASH MEMORY

K9F4G08U0A

K9K8G08U1A

Preliminary

Product Introduction

The K9F4G08U0A is a 4,224Mbit(4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64x8

columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-

dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made

up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists

of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program

and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-

sists of 4,096 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F4G08U0A.

The K9F4G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE

to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M byte physical space

requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the

command register. Table 1 defines the specific commands of the K9F4G08U0A.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Read EDC Status is only available on Copy Back operation.

3. Any command between 11h and 81h is prohibited except 70h and FFh.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function 1st Cycle 2nd Cycle Acceptable Command during Busy

Read 00h 30h

Read for Copy Back 00h 35h

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Two-Plane Page Program

(3)

80h---11h 81h---10h

Copy-Back Program 85h 10h

Two-Plane Copy-Back Program

(3)

85h---11h 81h---10h

Block Erase 60h D0h

Two-Plane Block Erase 60h---60h D0h

Random Data Input

(1)

85h -

Random Data Output

(1)

05h E0h

Read Status 70h O

Read EDC Status

(2)

7Bh O

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