Vivado 10G Ethernet PCS/PMA IP User Guide for Design and Implementation

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本资源是一份名为"pg068-ten-gig-eth-pcs-pma.pdf"的用户手册，专注于10G以太网PCS（Physical Coding Sublayer）和PMA（Physical Medium Attachment）的Vivado Design Suite中的LogiCORE IP产品。这份文档版本为v6.0，发布日期为2021年2月4日，由Xilinx提供。 1. **IP事实与概述**: - 用户手册首先介绍了产品概览，包括设计过程导航、核心功能概述以及应用领域。它提到了此设计可能不支持的某些功能，并对许可证和订购流程进行了概述。 2. **产品规格**: - 该章节详细列出了产品遵循的标准，如10G Ethernet标准。性能参数包括数据传输速率、吞吐量和时延等。资源利用率部分解释了核心占用的硬件资源，包括逻辑资源和接口配置。端口描述则涵盖了接收器和发送器的连接细节。 3. **设计流程**: - 设计步骤分为定制和生成核心、约束核心、仿真、综合与实施四个阶段。指南提供了通用设计准则，如时钟管理、复位处理、共享逻辑的设计方法以及与核心的接口设计。此外，还特别关注了DRP接口和接收器终端的具体实现，以及特殊设计注意事项。 4. **详细示例设计**: - 章节涵盖了一个实际设计的例子，包括核心支持层的构建，以及如何在设计中整合和利用这些组件。 5. **测试与验证**: - 在附录A中，手册提供了关于验证、UNH（Universal Network Harness）测试和互操作性的详细信息，强调了模拟环境在设计验证过程中的重要性。这份用户手册是工程师在设计10G以太网接口时的重要参考资料，无论是了解技术背景、遵循规范、还是进行具体设计和测试，都能从中找到关键信息和指导。通过学习和应用这些内容，设计师可以确保他们的10G以太网接口实现符合高性能和兼容性要求。

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Chapter 2: Product Specification

Shared Logic Included in Example Design

If Include Shared Logic in example design is selected during the core customization,

circuits for clock and reset management are included in the top-level example design

sources. These can include clock generators, reset synchronizers, or other circuits that can

be useful in your particular application. Table 2-6 shows the ports on the core that are

associated with clocks and resets.

Table 2-6: Clock and Reset Ports—Shared Logic in Example Design

Signal Name Direction Description

coreclk In

This clock is used to clock the TX datapath and management logic in

7 series devices and for 10GBASE-KR in UltraScale devices. In

UltraScale devices for 10GBASE-R this clock is used only as a free

running clock source for reset logic associated with the transceiver.

txusrclk, txusrclk2 In

Connected to the TXUSRCLK and TXUSRCLK2 input ports of the

transceiver, these clocks are derived from the TXOUTCLK from the

transceive r . In UltraScale devices for 10 G B A SE-R txusrclk2 is used to

clock the transmit datapath and management logic.

dclk

(1)

Management/DRP clock: this clock can be any rate that is valid for

the applicable transceiver DRPCLK.

areset In Asynchronous (master) reset

(2)

txoutclk Out

TXOUTCLK from the transceiver used in the shared clock generation

logic

rxrecclk_out Out RXOUTCLK from the transceiver

areset_coreclk In Synchronous reset in the coreclk domain

gttxreset In Transceiver TX reset signal in the coreclk domain

gtrxreset In Transceiver RX reset signal in the coreclk domain

qplllock In Transceiver QPLL Lock signal for 7 series devices

qplloutclk In Transceiver QPLL clock for 7 series devices

qplloutrefclk In Transceiver QPLL refclk for 7 series devices

qpll0lock In Transceiver QPLL lock signal for UltraScale devices

qpll0outclk In Transceiver QPLL clock for UltraScale devices

qpll0outrefclk In Transceiver QPLL refclk for UltraScale

devices

reset_counter_done In

Indication that 500 ns have passed after configuration was complete

tx_resetdone Out Transceiver TX reset-done

rx_resetdone Out Transceiver RX reset-done

reset_tx_bufg_gt Out

Control from core to the BUFG_GT in the shared logic. Only for

64-bit datapath cores on UltraScale devices

Send Feedback

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Chapter 2: Product Specification

Shared Logic Included in Core

If Include Shared Logic in core is selected during core customization, most of the clocking

and reset blocks are included within the core. Table 2- 7 shows the ports on the core that are

associated with these clocks and resets, which can be reused by other user logic or IP cores.

qpll0reset Out

For UltraScale

devices, a reset signal from the core to the QPLL

located in the shared logic.

Notes:

1. For UltraScale devices the DCLK must be free-running and the frequency must be kept less than or equal to the

maximum DRPCLK frequency specified for the transceiver type or the TXUSRCLK2 frequency, which is 156.25 MHz

for 64-bit datapaths.

2. This reset also resets all management registers.

Table 2-7: Clock and Reset Ports—Shared Logic in Core

Signal Name Direction Description

refclk_p, refclk_n In Differential clock input (for transceiver)

dclk

(1)

Management/DRP clock: this clock can be any rate that is valid for

the applicable transceiver drpclk

reset In Asynchronous master reset

(2)

resetdone_out Out

Combined transceiver reset-done indication (in the coreclk_out

domain)

coreclk_out Out

This is used to clock the TX datapath and management logic in

7 series devices and for 10GBASE-KR in UltraScale devices. In

UltraScale

devices for 10GBASE-R this clock is used only as a free

running clock source for reset logic associated with the

transceiver.

qplllock_out Out Lock indication from QPLL block in core for 7 series devices

qplloutclk_out Out QPLL output clock from QPLL block in core for 7 series devices

qplloutrefclk_out Out

QPLL output reference clock from QPLL block in core for 7 series

devices

qpll0lock_out Out Lock indication from QPLL block in core for UltraScale

architecture

qpll0outclk_out Out QPLL output clock from QPLL in core for UltraScale

architecture

qpll0outrefclk_out Out

QPLL output reference clk from QPLL in core for UltraScale

architecture

txusrclk_out Out txusrclk from shared logic block in core

txusrclk2_out Out

txusrclk2 from shared logic block in core. This is used to clock the

TX datapath and management logic in UltraScale

devices for

10GBASE-R designs.

rxrecclk_out Out

RXOUTCLK from the GT output which is used to clock the receive

datapath in the core.

Table 2-6: Clock and Reset Ports—Shared Logic in Example Design (Cont’d)

Signal Name Direction Description

Send Feedback

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PG068 February 4, 2021 www.xilinx.com

Chapter 2: Product Specification

10GBASE-KR Training Interface

In Virtex-7, and UltraScale devices, in 10GBASE-KR only, an external training algorithm can

optionally be connected to the training interface, which allows access to both the 802.3

registers in the core and the DRP registers in the transceiver. Table 2- 8 shows the ports on

the core that are associated with that interface.

areset_datapathclk_out Out

reset signal synchronized to the TX datapath clock which is the

free-running coreclk_out for 7 series devices and 10GBASE-KR

designs for UltraScale devices or the txusrclk2_out for UltraScale

devices in 10GBASE-R designs.

areset_coreclk_out Out

reset signal synchronized to the free-running coreclk_out;

UltraScale devices only

gttxreset_out Out

Signal that is used to reset the TX side of the transceiver,

synchronized to coreclk_out

gtrxreset_out Out

Signal that is used to reset the RX side of the transceiver,

synchronized to coreclk_out

txuserrdy_out Out

Transceiver control signal equivalent to the QPLLLOCK signal,

synchronized to txusrclk2_out

reset_counter_done_out Out

Indication that 500 ns have passed after configuration or 'master'

reset, synchronized to coreclk_out

Notes:

1. For UltraScale devices the DCLK must be free-running and the frequency must be kept less than or equal to the

maximum DRPCLK frequency specified for the transceiver type or the TXUSRCLK2 frequency, which is 156.25 MHz

for 64-bit datapaths.

2. This reset also resets all management registers.

Table 2-8: Training Interface Ports

Signal Name Direction Description

training_enable In

Signal from external training algorithm to enable the training

interface. This should not be confused with the IEEE register

1.150.1–Training Enable. A rising edge on training_enable

initiates a register access.

training_addr[20:0] In

DEVAD for 802.3 registers

training_rnw In Read/Write_bar signal from training algorithm

training_ipif_cs In Select access to 802.3 registers in the core

(1)

training_drp_cs In Select access to DRP registers in the transceiver

training_rddata[15:0] Out Read data from DRP or 802.3 registers

training_rdack Out Read Acknowledge signal to external training algorithm

Table 2-7: Clock and Reset Ports—Shared Logic in Core (Cont’d)

Signal Name Direction Description

Send Feedback

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